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PDF ISL83204A Data sheet ( Hoja de datos )

Número de pieza ISL83204A
Descripción High Frequency Full Bridge FET Driver
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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®
Data Sheet
March 20, 2007
ISL83204A
FN6397.2
60V/2.5A Peak, High Frequency Full Bridge
FET Driver
The ISL83204A is a high frequency, medium voltage Full
Bridge N-Channel FET driver IC, available in 20 lead plastic
SOIC and DIP packages. The ISL83204A includes an input
comparator used to facilitate the “hysteresis” and PWM
modes of operation. Its HEN (high enable) lead can force
current to freewheel in the bottom two external power
MOSFETs, maintaining the upper power MOSFETs off.
Since it can switch at frequencies up to 1MHz, the
ISL83204A is well suited for driving Voice Coil Motors,
switching power amplifiers and power supplies.
ISL83204A can also drive medium voltage brush motors,
and two ISL83204As can be used to drive high performance
stepper motors, since the short minimum “on-time” can
provide fine micro-stepping capability.
Short propagation delays of approximately 55ns maximize
control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion, resulting
in precise control of the driven load.
Ordering Information
www.DataSheet4U.com
TEMP
PART
PART
RANGE
NUMBER
MARKING
(°C)
PKG.
PACKAGE DWG. #
ISL83204AIPZ ISL83204AIPZ -40 to +85 20 Ld PDIP E20.3
(Note)
(Pb-Free)
ISL83204AIBZ* ISL83204AIBZ -40 to +85 20 Ld SOIC M20.3
(Note)
(Pb-Free)
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• Drives N-Channel FET Full Bridge Including High Side
Chop Capability
• Bootstrap Supply Max Voltage to 75VDC
• Drives 1000pF Load at 1MHz in Free Air at +50°C with
Rise and Fall Times of Typically 10ns
• User-Programmable Dead Time
• Charge-Pump and Bootstrap Maintain Upper Bias
Supplies
• DIS (Disable) Pin Pulls Gates Low
• Input Logic Thresholds Compatible with 5V to 15V Logic
Levels
• Very Low Power Consumption
• Undervoltage Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Medium/Large Voice Coil Motors
• Full Bridge Power Supplies
• Switching Power Amplifiers
• Uninterruptible Power Supplies
• High Performance Motor Controls
• Noise Cancellation Systems
• Battery Powered Vehicles
Pinout
ISL83204A
(20 LD PDIP, 20 LD SOIC)
TOP VIEW
BHB 1
HEN 2
DIS 3
VSS 4
OUT 5
IN+ 6
IN- 7
HDEL 8
LDEL 9
AHB 10
20 BHO
19 BHS
18 BLO
17 BLS
16 VDD
15 VCC
14 ALS
13 ALO
12 AHS
11 AHO
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

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ISL83204A pdf
ISL83204A
Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100k, and
TA = +25°C, Unless Otherwise Specified (Continued)
TJ = +25°C
TJ = -40°C to +125°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN TYP MAX MIN MAX UNITS
Voltage Gain
AVOL
- 25 - - - V/mV
OUT High Level Output
Voltage
VOH
IN+ >IN-, IOH = -250μA
VDD - 0.4
-
- VDD - 0.5 -
V
OUT Low Level Output
Voltage
VOL IN+ <IN-, IOL = +250μA
- - 0.4 - 0.5 V
Low Level Output Current
High Level Output Current
INPUT PINS: DIS
IOL VOUT = 6V
IOH VOUT = 6V
6.5 14 19
-17 -10
-3
6 20 mA
-20 -2.5 mA
Low Level Input Voltage
High Level Input Voltage
Input Voltage Hysteresis
VIL Full Operating Conditions
VIH Full Operating Conditions
- - 1.0 - 0.8 V
2.5 - - 2.7 - V
- 35 - - - mV
Low Level Input Current
High Level Input Current
INPUT PINS: HEN
IIL
VIN = 0V, Full Operating Conditions -130
-100
-75
IIH VIN = 5V, Full Operating Conditions -1 - +1
-135
-10
-65 μA
+10 μA
Low Level Input Voltage
High Level Input Voltage
Input Voltage Hysteresis
VIL Full Operating Conditions
VIH Full Operating Conditions
- - 1.0 - 0.8 V
2.5 - - 2.7 - V
- 35 - - - mV
Low Level Input Current
IIL VIN = 0V, Full Operating Conditions
High Level Input Current
IIH VIN = 5V, Full Operating Conditions
TURN-ON DELAY PINS: LDEL AND HDEL
-260
-1
-200
-
-150
+1
-270
-10
-130
+10
μA
μA
LDEL, HDEL Voltage
VHDEL,V IHDEL = ILDEL = -100μA
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO
4.9 5.1 5.3 4.8 5.4 V
Low Level Output Voltage
High Level Output Voltage
Peak Pullup Current
Peak Pulldown Current
Under Voltage, Rising
Threshold
VOL
IOUT = 100mA
VCC - VOH IOUT = -100mA
IO+ VOUT = 0V
IO- VOUT = 12V
UV+
0.7 0.85 1.0 0.5 1.1 V
0.8 0.95 1.1 0.5 1.2 V
1.7 2.6 3.8 1.4 4.1 A
1.7 2.4 3.3 1.3 3.6 A
8.1 8.8 9.4 8.0 9.5 V
Under Voltage, Falling
Threshold
UV-
7.6 8.3 8.9 7.5 9.0 V
Under Voltage, Hysteresis
HYS
0.25 0.4 0.65
0.2
0.7 V
5 FN6397.2
March 20, 2007

5 Page





ISL83204A arduino
ISL83204A
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V,
RHDEL = RLDEL = 100k, and TA = +25°C, Unless Otherwise Specified. (Continued)
450 80
70
425
60
400 50
375
350
-50
-25
0 25 50 75 100 125 150
JUNCTION TEMPERATURE (°C)
FIGURE 16. tTREF-PW REFRESH PULSE WIDTH vs
TEMPERATURE
40
30
20
-40 -20
0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 17. DISABLE TO LOWER ENABLE tDLPLH
PROPAGATION DELAY vs TEMPERATURE
90
80
70
60
50
40
-40 -20
0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 18. UPPER TURN-OFF PROPAGATION DELAY tHPHL
vs TEMPERATURE
90
80
70
60
50
40
-40 -20
0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 19. UPPER TURN-ON PROPAGATION DELAY tHPLH
vs TEMPERATURE
90
80
70
60
50
40
-40 -20
0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 20. LOWER TURN-OFF PROPAGATION DELAY tLPHL
vs TEMPERATURE
11
90
80
70
60
50
40
-40 -20
0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 21. LOWER TURN-ON PROPAGATION DELAY tLPLH
vs TEMPERATURE
FN6397.2
March 20, 2007

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