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PDF SY88793V Data sheet ( Hoja de datos )
| Número de pieza | SY88793V | |
| Descripción | PECL LOW-POWER LIMITING POST AMPLIFIER | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SY88793V (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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Micrel, Inc.
3.3V/5V 622Mbps PECL LOW-POWER
LIMITING POST AMPLIFIER WITH TTL
SIGNAL DETECT
SY88793V
SY88793V
FEATURES
s Single 3.3V or 5V power supply
s Up to 622Mbps operation
s Low noise PECL data outputs
s Chatter-free TTL Signal Detect (SD) output
s TTL EN input
s Programmable SD level set (SDLVL)
s Available in a tiny 10-pin MSOP (3mm) package
APPLICATIONS
s 622Mbps SONET/SDH
s Small form factor transceivers
s High-gain line driver and line receiver
DESCRIPTION
The SY88793V low-power limiting post amplifier is
designed for use in fiber optic receivers. The device connects
to typical transimpedance amplifiers (TIAs). The linear signal
output from TIAs can contain significant amounts of noise
and may vary in amplitude over time. The SY88793V
quantizes these signals and outputs PECL level waveforms.
The SY88793V operates from a single +3.3V or +5V
power supply, over temperatures ranging from –40°C to
+85°C. With its wide bandwidth and high gain, signals with
data rates up to 622Mbps and as small as 5mVp-p can be
amplified to drive devices with PECL inputs.
The SY88793V generates a TTL SD output. A
programmable signal-detect level set pin (SDLVL) sets the
sensitivity of the input amplitude detection. SD asserts high
if the input amplitude rises above the threshold set by SDLVL
and deasserts low otherwise. EN deasserts the true output
signal without removing the input signal. Typically 6dB SD
hysteresis is provided to prevent chattering.
www.DataSheet4U.com
TYPICAL APPLICATIONS CIRCUIT
From
Transimpedance
Amp.
0.1µF
0.1µF
50Ω
SD
DIN
/DIN
50Ω
VCC
EN
SY88793V
DOUT
/DOUT
SDLVL VREF
Rpd
0.1µF
0.1µF
Rpd
To
CDR
GND VCC
100kΩ 0.1µF
GND
For 3.3V, Rpd = 120Ω
For 5V, Rpd = 220Ω
M9999-072505
[email protected] or (408) 955-1690
1
Rev.: B Amendment: /0
Issue Date: July 2005
1 page  
Micrel, Inc.
SY88793V
DETAILED DESCRIPTION
The SY88793V low-power limiting post amplifier operates
from a single +3.3V or +5V power supply, over temperatures
from –40°C to +85°C. Signals with data rates up to 622Mbps
and as small as 5mVp-p can be amplified. Figure 1 shows
the allowed input voltage swing. The SY88793V generates
an SD output. SDLVL sets the sensitivity of the input
amplitude detection.
Input Amplifier/Buffer
Figure 2 shows a simplified schematic of the SY88793V's
input stage. The high-sensitivity of the input amplifier allows
signals as small as 5mVPP to be detected and amplified.
The input amplifier allows input signals as large as
1800mVPP. Input signals are linearly amplified with a typically
38dB differential voltage gain. Since it is a limiting amplifier,
the SY88793V outputs typically 1500mVPP voltage-limited
waveforms for input signals that are greater than 18mVPP.
Applications requiring the SY88793V to operate with high-
gain should have the upstream TIA placed as close as
possible to the SY88793V’s input pins to ensure the best
performance of the device.
Output Buffer
The SY88793V’s PECL output buffer is designed to drive
50Ω lines. The output buffer requires appropriate termination
for proper operation. An external 50Ω resistor to VCC–2V
for each output pin provides this. Figure 3 shows a simplified
schematic of the output stage and includes an appropriate
termination method.
Signal-Detect
The SY88793V generates a chatter-free SD open-collector
TTL output with internal 6.75kΩ pullup resistor as shown in
Figure 4. SD is used to determine that the input amplitude
is large enough to be considered a valid input. SD asserts
high if the input amplitude rises above the threshold set by
SDLVL and deasserts low otherwise. SD can be fed back to
the enable (EN) input to maintain output stability under a
loss of signal condition. EN deasserts the true output signal
without removing the input signals. Typically 6dB SD
hysteresis is provided to prevent chattering.
Signal-Detect Level Set
A programmable SD level set pin (SDLVL) sets the
threshold of the input amplitude detection. Connecting an
external resistor between VCC and SDLVL sets the voltage
at SDLVL. This voltages ranges from VCC to VREF. The
external resistor creates a voltage divider between VCC and
VREF as shown in Figure 5. If desired, an appropriate
external voltage may be applied rather than using a resistor.
The smaller the external resistor, implying a smaller voltage
difference from SDLVL to VCC, the smaller the SD sensitivity.
Hence, larger input amplitude is required to assert SD.
“Typical Operating Characteristics” shows the relationship
between the input amplitude detection sensitivity and the
SDLVL voltage.
Hysteresis
The SY88793V provides typically 6dB SD electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V2IN/R for an
electrical signal. Hence the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and
hence the ratios change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the datasheet. The SY88793V provides typically 3dB SD
optical hysteresis. As the SY88793V is an electrical device,
this datasheet refers to hysteresis in electrical terms. With
6dB SD hysteresis, a voltage factor of two is required to
assert or deassert SD.
M9999-072505
[email protected] or (408) 955-1690
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet SY88793V.PDF ] | |
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