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PDF SY58627L Data sheet ( Hoja de datos )
| Número de pieza | SY58627L | |
| Descripción | Backplane Receive Buffer | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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SY58627L
DC-to-6.4Gbps Backplane Receive Buffer with
Four Stage Programmable Equalization
and DC-Offset Control
Preliminary
General Description
The SY58627L high-speed, low jitter receive buffer is
optimized for backplane and transmission line data-path
Precision Edge®
management applications. The SY58627L is capable of Features
receiving serial data up to 6.4Gbps across up to 36
inches of FR4.
The SY58627L differential input includes Micrel’s
unique, 3-pin input termination architecture that directly
interfaces to any differential signal as small as 100mVpk
(AC- or DC-coupled) without any termination resistor
• Selectable equalizing network to optimize incoming
data eye pattern
• Four selectable equalization levels
• Receives up to 36” FR4 PCB trace, or longer
combinations of FR4+cable+interconnect
networks in the signal path. The outputs are 50Ω • DC through 6.4Gbps data rate throughput
source-terminated CML optimized to drive 400mVpk into • Integrated loopback capability
50Ω (100Ω load across the output pair). The I/O
termination is connected to a dedicated VTT pin for
added bias flexibility.
• Unique, flexible I/O:
- Patented, Internal termination to VTTIN pin
interfaces to any differential AC- or DC-coupled
The SY58627L receiver input provides four levels of
signals
equalization to compensate for degraded signals
- 50Ω source-terminated CML outputs minimize
resulting from transmission losses. The equalization is
programmed with a three-bit interface.
www.DataSheet4U.com
-
The SY58627L operates at 3.3V ±10% supply and is
guaranteed over the full industrial temperature range of
-40°C to +85°C. The SY58627L is part of Micrel’s high-
-
-
round-trip reflections
Wide input voltage range: 100mV to 1.3VPK
Output disable
DC-offset control with VTT I/O
speed, Precision Edge® product line.
• Input Loss-of-Signal
All data sheets and support documentation can be
found on Micrel’s web site at: www.micrel.com.
- Hysteresis included
• 3.3V ±10% supply voltage
• -40°C to +85°C temperature range
• Available in 32-pin (5mm x 5mm) MLFTM package
Applications
• ATE, T&M backplane management
• Serial backplane management
• Combination FR4+cable+interconnect receiver
• Fibre Channel, GigE, SONET/SDH data transmission
• Electrical interface and interconnect applications that
require DC-offset control
Precison Edge is a registered trademark of Micrel, Inc.
MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
January 2006
M9999-012606-A
[email protected] or (408) 955-1690
1 page  
Micrel, Inc.
SY58627L
Pin Description (Continued)
Pin Number
13, 14
21, 19
26
20
28
29
30
1, 8, 9, 16, 17,
24, 25
2, 5, 18, 22, 31,
32
Pin Name
RXLBQ,
/RXLBQ
RXQ,
/RXQ
LOS
VTTOUT
EQ2( MSB)
EQ1
EQ0
VCC
VEE,
Exposed Pad
Pin Function
Receiver loopback CML compatible output pair. When the SY58627L is in local
Loopback mode (LBSEL = 1), RXLBQ output is directed from TXLBIN (no
equalization). When the SY58627L is in normal mode (LBSEL = LOW) and the
RXLBQ output is not required, disable the RXLBQ output (/RXLBEN = HIGH) to
minimize switching noise. This differential output pair is optimized to drive 400mVPK
swing into a 50Ω load (100Ω across the pair). The RXLBQ output pair includes 50Ω
internal source termination resistors.
Receiver differential CML compatible output pair: This CML-compatible output pair is
the equalized signal seen at the RXIN input pair and is optimized to drive 400mVPK
swing into a 50Ω load (100Ω across the pair). The RXQ output pair includes 50Ω
internal source termination resistors. When the SY58627L is in Loopback mode
(LBSEL = HIGH), then the RXQ output signal is directed from the unequalized
TXLBIN input.
Please contact factory Applications Engineers.
Output termination center-tap: Each side of the RXQ differential output pair
terminates to the VTTOUT pin through 50Ω. The VTTOUT pin provides a center-tap
to the output termination network for maximum interface flexibility, and DC-offset
capability. Please refer to the “CML Output Interface Applications” section for more
details.
TTL/CMOS (or VTH controlled) compatible, 3-bit control interface. There are four
levels of equalization, as shown in the “Equalization Select Truth Table.” When the
MSB is logic HIGH, the RXQ output pair will not include any equalization.
000 = lowest equalization setting
001 = medium equalization setting
010 = medium-high equalization setting
011 = highest equalization setting
1XX = equalization bypass
Positive Power Supply: Connect to +3.3V power supply. Bypass with 0.1µF//0.01µF
low ESR capacitors as close to VCC pins as possible.
Ground: Ground pins and exposed pad must be connected to the same ground
plane.
Equalization Select Truth Table
Disable EQ
(MSB = EQ2)
0
0
0
0
1
Equalization
Select (EQ1)
0
0
1
1
X
Equalization
Select (EQ0)
0
1
0
1
X
Typical FR4 Length
9”
18”
24”
36”
NA
Equalization
Low
Medium Low
Medium High
High
Disabled
Janaury 2006
5 M9999-012606-A
[email protected] or (408) 955-1690
5 Page 
Micrel, Inc.
Figure 2c. Link Side Loopback Mode
SY58627L
LBSEL
0
0
0
0
1
1
1
1
/RXLBEN
0
0
1
1
0
0
1
1
/RXEN
0
1
0
1
0
1
0
1
RXQ
RXIN
0
RXIN
0
TXLBIN
0
TXLBIN
0
RXLBQ
RXIN
RXIN
0
0
TXLBIN
TXLBIN
0
0
Table 1. Transmit Loopback Control Signal
Figure 3. Loopback Control
Janaury 2006
11 M9999-012606-A
[email protected] or (408) 955-1690
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet SY58627L.PDF ] | |
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