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PDF SY58605U Data sheet ( Hoja de datos )
| Número de pieza | SY58605U | |
| Descripción | LVDS Buffer | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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SY58605U
3.2Gbps Precision, LVDS Buffer with
Internal Termination and Fail Safe Input
General Description
The SY58605U is a 2.5V, high-speed, fully differential
LVDS buffer optimized to provide less than 10pspp total
jitter. The SY58605U can process clock signals as fast
as 2GHz or data patterns up to 3.2Gbps.
Features
• Precision 325mV LVDS buffer
Precision Edge®
The differential input includes Micrel’s unique, 3-pin
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC- or DC-coupled)
as small as 100mV (200mVpp) without any level-shifting
or termination resistor networks in the signal path. For
AC-coupled input interface applications, an integrated
voltage reference (VREF-AC) is provided to bias the VT pin.
The output is 325mV LVDS, with rise/fall times
guaranteed to be less than 100ps.
• Guaranteed AC performance over temperature and
voltage:
– DC-to > 3.2Gbps throughput
– <300ps typical propagation delay (IN-to-Q)
– <100ps rise/fall times
• Fail Safe Input
– Prevents output from oscillating when input is
invalid
The SY58605U operates from a 2.5V ±5% supply and is • Ultra-low jitter design
guaranteed over the full industrial temperature range
– <1psRMS cycle-to-cycle jitter
(LSsh–wViYg4iP5hn0E8-g°sC6sCp0Lert4oeeUdso+,p,u8ePtb5cpru°etuiCfvctfsee)is.,rliysoF.cnooTwrEnhiatdsehpigdpeSe4l®iYrc0p5a0rM8tmoio6idVcn0urs5ecUaltt’hsnliaindsteSr.p8Yea0q5r0ut8mi6ore0Vf 3MCUoMicurLwtaepwnwlou’.dDsrtataSheet•4U.c–––Homig<<<h111-s00ppppseRsseMPPPPSd
total jitter
random jitter
deterministic
LVDS output
jitter
Data sheets and support documentation can be found
on Micrel’s web site at: www.micrel.com.
• 2.5V ±5% power supply operation
• Industrial temperature range: –40°C to +85°C
• Available in 8-pin (2mm x 2mm) MLF® package
Functional Block Diagram
Applications
• All SONET clock and data distribution
• Fibre Channel clock and data distribution
• Gigabit Ethernet clock and data distribution
• Backplane distribution
Markets
• Storage
• ATE
• Test and measurement
• Enterprise networking equipment
• High-end servers
• Access
• Metro area network equipment
Precision Edge is a registered trademark of Micrel, Inc.
MLF and MicroLeadFrame are registered trademarks of Amkor Technology.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
September 2006
M9999-092606-A
[email protected] or (408) 955-1690
1 page  
Micrel, Inc.
SY58605U
AC Electrical Characteristics
VCC = +2.5V ±5%, RL = 100Ω across the outputs, Input tr/tf: <300ps; TA = –40°C to +85°C, unless otherwise stated.
Symbol
fMAX
tPD
tSkew
tJitter
tr, tf
Parameter
Maximum Frequency
Propagation Delay
IN-to-Q
Part-to-Part Skew
Data
Random Jitter
Deterministic Jitter
Clock
Cycle-to-Cycle Jitter
Total Jitter
Output Rise/Fall Times
(20% to 80%)
Duty Cycle
Condition
NRZ Data
VOUT > 200mV
VIN: 100mV-200mV
200mV-800mV
Note 8
Note 9
Note 10
Note 11
Note 12
At full output swing.
Differential I/O
Min Typ Max Units
3.2 Gbps
Clock 2.0
3
GHz
170 280 420 ps
130 200 300 ps
135 ps
1 psRMS
10 psPP
1 psRMS
10 psPP
35 60 100 ps
47 53 %
Notes:
8. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
9. Random jitter is measured with a K28.7 pattern, measured at ≤ fMAX.
10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern.
11. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,
where T is the time between rising edges of the output signal.
12. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by
more than the specified peak-to-peak jitter value.
September 2006
5 M9999-092606-A
[email protected] or (408) 955-1690
5 Page 
Micrel, Inc.
Input Interface Applications
SY58605U
Figure 4a. CML Interface
(DC-Coupled)
Option: May connect VT to VCC
Figure 4b. CML Interface
(AC-Coupled)
Figure 4c. LVPECL Interface
(DC-Coupled)
Figure 4d. LVPECL Interface
(AC-Coupled)
Figure 4e. LVDS Interface
Related Product and Support Documents
Part Number
SY58603U
SY58604U
HBW Solutions
Function
4.25Gbps Precision CML Buffer with
Internal Termination and Fail Safe Input
3.2Gbps Precision LVPECL Buffer with
Internal Termination and Fail Safe Input
New Products and Termination Application
Notes
Data Sheet Link
http://www.micrel.com/page.do?page=/product-
info/products/sy58603u.shtml
http://www.micrel.com/page.do?page=/product-
info/products/sy58604u.shtml
http://www.micrel.com/page.do?page=/product-
info/as/HBWsolutions.shtml
September 2006
11 M9999-092606-A
[email protected] or (408) 955-1690
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet SY58605U.PDF ] | |
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