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PDF SY58603U Data sheet ( Hoja de datos )
| Número de pieza | SY58603U | |
| Descripción | Precision CML Buffer | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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SY58603U
4.25Gbps Precision CML Buffer with Internal
Termination and Fail Safe Input
General Description
The SY58603U is a 2.5/3.3V, high-speed, fully
differential CML buffer optimized to provide less than
10pspp total jitter. The SY58603U can process clock
signals as fast as 2.5GHz or data patterns up to
Features
• Precision 400mV CML buffer
Precision Edge®
4.25Gbps.
• Guaranteed AC performance over temperature and
The differential input includes Micrel’s unique, 3-pin
voltage:
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC-coupled or DC-
coupled) as small as 100mV (200mVpp) without any
level-shifting or termination resistor networks in the
signal path. For AC-coupled input interface applications,
– DC-to >4.25Gbps throughput
– <300ps propagation delay (IN-to-Q)
– <85ps rise/fall times
• Fail Safe Input
an integrated voltage reference (VREF-AC) is provided to
– Prevents output from oscillating when input is
bias the VT pin. The output is 400mV CML, with
invalid
extremely fast rise/fall times guaranteed to be less than • Ultra-low jitter design
85ps.
– <1psRMS cycle-to-cycle jitter
T3iacnop.hd3npeuVslsiciSdtar±eYita1ir5ol08nt%h6tsee0m3tshSUpuaeYptrpo5alp8ryteue6qrr0aeau4ntiUerdresanaifLsgnroVedmgPuSE(–aaYC4r5aL028n°.6tC5oe0Vre5dtUoL±V5,o%D+vb8eSu5rsff°ueoCtprhus)pe.tplywwuFwfitwuoots.hDlrr,lataSheet•4U.co–––Hmigh<<<-111s00ppppseRsseMPPdPPS
total jitter
random jitter
deterministic
CML output
jitter
800mV and 325mV output swings respectively. The • 2.5V ±5% or 3.3V ±10% power supply operation
SY58603U is part of Micrel’s high-speed, Precision
Edge® product line.
Data sheets and support documentation can be found
• Industrial temperature range: –40°C to +85°C
• Available in 8-pin (2mm x 2mm) MLF® package
on Micrel’s web site at: www.micrel.com.
Applications
Functional Block Diagram
• Data Distribution: OC-48, OC-48+FEC, XAUI
• Backplane Buffering
• SONET clock or data distribution
• Fibre Channel clock or data distribution
• Gigabit Ethernet clock or data distribution
Markets
• Storage
• ATE
• Test and measurement
• Enterprise networking equipment
• High-end servers
• Access
• Metro area network equipment
Precision Edge is a registered trademark of Micrel, Inc.
MLF and MicroLeadFrame are registered trademarks of Amkor Technology
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
September 2006
M9999-092206-A
[email protected] or (408) 955-1690
1 page  
Micrel, Inc.
SY58603U
AC Electrical Characteristics
VCC = +2.5V ±5% or +3.3V ±10%, RL = 100Ω across the outputs, Input tr/tf: <300ps; TA = –40°C to +85°C, unless
otherwise stated.
Symbol
fMAX
tPD
tSkew
tJitter
tr, tf
Parameter
Maximum Frequency
Propagation Delay
IN-to-Q
Part-to-Part Skew
Data
Random Jitter
Deterministic Jitter
Clock
Cycle-to-Cycle Jitter
Total Jitter
Output Rise/Fall Times
(20% to 80%)
Duty Cycle
Condition
NRZ Data
VOUT > 200mV
VIN: 100mV-200mV
VIN: 200mV-800mV
Note 8
Note 9
Note 10
Note 11
Note 12
At full output swing.
Differential I/O
Min Typ Max Units
4.25 Gbps
Clock 2.5
3
GHz
150 250 350 ps
120 190 300 ps
100 ps
1 psRMS
10 psPP
1 psRMS
10 psPP
30 50 85 ps
47 53 %
Notes:
8. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
9. Random jitter is measured with a K28.7 pattern, measured at ≤ fMAX.
10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern.
11. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,
where T is the time between rising edges of the output signal.
12. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by
more than the specified peak-to-peak jitter value.
September 2006
5 M9999-092206-A
[email protected] or (408) 955-1690
5 Page 
Micrel, Inc.
Input Interface Applications
SY58603U
Figure 4a. CML Interface
(DC-Coupled)
Option: May connect VT to VCC
Figure 4b. CML Interface
(AC-Coupled)
Figure 4c. LVPECL Interface
(DC-Coupled)
Figure 4d. LVPECL Interface
(AC-Coupled)
Figure 4e. LVDS Interface
September 2006
11 M9999-092206-A
[email protected] or (408) 955-1690
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet SY58603U.PDF ] | |
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