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PDF AT43312A Data sheet ( Hoja de datos )
| Número de pieza | AT43312A | |
| Descripción | Self- and Bus-Bus-powered USB Hub Controller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Full Compliance with USB Spec Rev 1.1
• Four Downstream Ports
• Full-speed and Low-speed Data Transfers
• Bus-powered Controller
• Bus-powered or Self-powered Hub Operation
• Per Port Overcurrent Monitoring
• Individual Port Power Control
• USB Connection Status Indicators
• 5V Operation with On-chip 3.3V Format
• 32-lead SOIC and LQFP
• Green (Pb/Halide-free/RoHS Compliant) Package Options Available
Overview
Introduction
The AT43312A is a 5 port USB hub chip supporting one upstream and four down-
stream ports. The AT43312A connects to an upstream hub or Host/Root Hub via Port0
and the other ports connect to external downstream USB devices. The hub re-trans-
mits the USB differential signal between Port0 and Ports[1:4] in both directions. A USB
hub with the AT43312A can operate as a bus-powered or self-powered through chip’s
power mode configuration pin. In the self-powered mode, port power can be switched
or unswitched. Overcurrent reporting and port power control can be individual or glo-
bal. An on-chip power supply eliminates the need for an external 3.3V supply.
The AT43312A supports the 12-Mb/sec full speed as well as 1.5-Mb/sec slow speed
USB transactions. To reduce EMI, the AT43312A’s oscillator frequency is 6 MHz even
though some internal circuitry operates at 48 MHz.
www.DataSheet4U.com
The AT43312A consists of a Serial Interface Engine, a Hub Repeater, and a Hub
Controller.
Self- and Bus-
powered USB
Hub Controller
AT43312A
SOIC
PWR2
PWR3
PWR4
VCC5
VSS
OSC1
OSC2
LFT
TEST
OVC4
OVC3
OVC2
OVC1
LPSTAT
SELF/BUS
STAT4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 PWR1
31 DP4
30 DM4
29 DP3
28 DM3
27 VSS
26 DP2
25 DM2
24 CEXT
23 DP1
22 DM1
21 DP0
20 DM0
19 STAT1
18 STAT2
17 STAT3
LQFP Top View
DP3
DM4
DP4
PWR1
PWR2
PWR3
PWR4
VCC5
1
2
3
4
5
6
7
8
24 DMO
23 STAT1
22 STAT2
21 STAT3
20 STAT4
19 SELF/BUS
18 LPSTAT
17 OVC1
1255G–USB–05/06
1
1 page  
Signal Description
OSC1
OSC2
LFT
SELF/BUS
LPSTAT
DP0
DM0
DP[1:4]
DM[1:4]
OVC[1:4]
PWR[1:4]
STAT[1:4]
CEXT
TEST
VCC
VSS
AT43312A
Oscillator Input. Input to the inverting 6 MHz oscillator amplifier.
Oscillator Output. Output of the inverting oscillator amplifier.
PLL Filter. For proper operation of the PLL, this pin should be connected through a
2.2 nF capacitor in parallel with a 100Ω resistor in series with a 10 nF capacitor to
ground (VSS).
Hub Power Mode. Input signal that sets the bus or self-powered mode operation. A high
on this pin enables the self-powered mode, a low enables the bus-powered mode.
Local Power Status. In the self-powered mode, this is an input pin that should be con-
nected to the local power supply through a 47 kΩ resistor. The voltage on this pin is
used by the chip for reporting the condition of the local power supply. In the bus-pow-
ered mode, this pin is not used.
Upstream Plus USB I/O. This pin should be connected to CEXT through an external
1.5 kΩ pull-up resistor. DP0 and DM0 form the differential signal pin pairs connected to
the Host Controller or an upstream Hub.
Upstream Minus USB I/O.
Port Plus USB I/O. This pin should be connected to VSS through an external 15 kΩ
resistor. DP[1:4] and DM[1:4] are the differential signal pin pairs to connect downstream
USB devices.
Port Minus USB I/O. This pin should be connected to VSS through an external 15 kΩ
resistor
Overcurrent. This is the input signal used to indicate to the AT43312A that an overcur-
rent is detected at the port. If OVCx is asserted, AT43312A will assert the PWRx pin and
report the status to the USB Host.
Power Switch. This is an output signal used to enable or disable the external voltage
regulator supplying power to a port. PWRx is de-asserted when a power supply problem
is detected at OVCx.
Connect Status. This is an output pin indicating that a port is properly connected. STATx
is asserted when the port is enabled.
External Capacitor. For proper operation of the on chip regulator, a 0.27 µF capacitor
must be connected to this pin.
Test. This pin should be connected to a logic high for normal operation.
5V Power Supply.
Ground.
1255G–USB–05/06
5
5 Page 
AT43312A
Oscillator and Phase-
Locked-Loop
An IN Token packet from the Host to Endpoint 1 indicates a request for port change sta-
tus. If the Hub has not detected any change on its ports, or any changes in itself, then all
bits in this register will be 0 and the Hub Controller will return a NAK to requests on
Endpoint1. If any of bits 0 - 4 is 1, the Hub Controller will transfer the whole byte. The
Hub Controller will continue to report a status change when polled until that particular
change has been removed by a ClearPortFeature request from the Host. No status
change will be reported by Endpoint 1 until the AT43312A has been enumerated and
configured by the Host via Endpoint 0.
All the clock signals required to run the AT43311 are derived from an on-chip oscillator.
To reduce EMI and power dissipation in the system, the oscillator is designed to operate
with a 6 MHz crystal. An on-chip PLL generates the high frequency for the clock/data
separator of the Serial Interface Engine. In the suspended state, the oscillator circuitry is
turned off. To assure quick startup, a crystal with a high Q, or low ESR, should be used.
To meet the USB hub frequency accuracy and stability requirements for hubs, the crys-
tal should have an accuracy and stability of better than 100 PPM. Even though the
oscillator circuit would work with a ceramic resonator, its use is not recommended
because a resonator would not have the frequency accuracy and stability.
A 6 MHz parallel resonance quartz crystal with a load capacitance of approximately
10 pF is recommended. The oscillator is a special low-power design and in most cases
no external capacitors and resistors are necessary. If the crystal requires a higher value
capacitance, external capacitors can be added to the two terminals of the crystal and
ground to meet the required value. If the crystal used cannot tolerate the drive levels of
the oscillator, a series resistor between OSC2 and the crystal pin is recommended.
The clock can also be externally sourced. In this case, connect the clock source to the
OSC1 pin, while leaving OSC2 pin floating. The switching level at the OSC1 pin can be
as low as 0.47V (see Table 8) and a CMOS device is required to drive this pin to main-
tain good noise margins at the low switching level.
Figure 4. Oscillator and PLL Connections
U1
Y1
6.000 MHz
R1
100
C1
10nF
OSC1
OSC2 AT43312A
LFT
C2
2nF
1255G–USB–05/06
For proper operation of the PLL, an external RC filter consisting of a series RC network
of 100Ω and 10 nF in parallel with a 2 nF capacitor must be connected from the LFT pin
to VSS.
To provide the best operating condition for the AT43312A, careful consideration of the
power supply connections are recommended. Use short, low-impedance connections to
all power supply lines: VCC5, and VSS. Use sufficient decoupling capacitors to reduce
noise: 0.1 µF decoupling capacitors of high quality, soldered as close as possible to the
package pins are recommended.
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AT43312A.PDF ] | |
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