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PDF CMX865A Data sheet ( Hoja de datos )
| Número de pieza | CMX865A | |
| Descripción | DTMF Codec | |
| Fabricantes | CML | |
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CMX865A
Telecom Signalling
Device
D/865A/3 February 2007
Provisional Issue
CMX865A – DTMF CODEC AND TELECOM SIGNALLING COMBO
Features
• V.23 1200/75, 1200/1200, 75, 1200 bps FSK
• Bell 202 1200/150, 1200/1200, 150, 1200 bps FSK
• V.21 or Bell 103 300/300 bps FSK
• Low Voice Falsing DTMF Decoder
• DTMF/Tones Transmit and Receive
• Low Power - High Performance
Applications
• Wireless Local Loops
• SMS Phones
• Security Systems
• Remote Utility Meter Reading
• Industrial Control Systems
• Pay-Phones
• Set-Top Boxes
LINE
LINE
INTERFACE
CMX865A
TX USART
FSK MODULATOR
TONE / DTMF GENEwRwAw.TDaOtaRSheet4U.com
RX USART
FSK RECEIVER
TONE / DTMF DETECTOR
C-BUS
SERIAL
INTERFACE
HOST
µC
1. Brief Description
The CMX865A is a multi-standard modem for use in Wireless Local Loop, Short Message Service
telephone based information and telemetry systems. Flexible line driver, hybrid and receiver circuits are
integrated on chip, requiring only passive external components to build a 2 or 4-wire line interface.
A high-quality DTMF decoder with excellent immunity to falsing on voice and a standard DTMF encoder
are included. Alternatively, these blocks can be used to transmit and detect user-specific, programmed
single and dual-tone signals, simple melodies, call progress signals or modem calling and answering
tones.
Host control and data transfer is via a high-speed serial bus that operates in normal and Powersave
modes and which is compatible with most simple types of µC serial interface. An embedded USART
allows multi-format asynchronous data and unformatted synchronous data to be received or transmitted
as 8-bit bytes.
The CMX865A operates from a single 3.0V to 3.6V supply over a temperature range of -40°C to +85°C
and is available in 16-pin SOIC (D4) and 16-pin TSSOP (E4) packages.
© 2007 CML Microsystems Plc
1 page  
Telecom Signalling Device
CMX865A
4. External Components
VDD
C1
R1
VSSD C2
VDEC
XTALN
X1 XTAL
IRQN
1 16 REPLY DATA
SERIAL CLOCK
2 15
3 14 COMMAND DATA
4 CMX865A 13 CSN
C-BUS
to/from
µC
Rx Line
Interface
VSSD
VSSA
RXAN
RXFB
5
6
7
8
12 VDD
11 TXA
10 TXAN
9 VBIAS
C3
Tx Line
Interface
VSSA
+
C6
VDEC
C7
VSSD VSSD
+
C5
VDD
C4
VSSA VSSA
Ground plane
connection
VSSA VSSD
R1 68kΩ
C1, C2
22pF
X1 6.144MHz (+ 300ppm)
C3, C4, C7 100nF
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C5, C6
10uF
Resistors ±5%, capacitors ±20% unless otherwise stated.
Figure 2 Recommended External Components for a Typical Application
This device is capable of detecting and decoding small amplitude signals. To achieve this, VDD, VDEC and
VBIAS should be decoupled close to the package and the receive path protected from extraneous in-band
signals.
It is recommended that the printed circuit board is laid out with low impedance analogue and digital
ground planes. The analogue ground plane should be a solid area under the analogue section of the
device defined by pins 6 – 11, plus associated external components. The digital ground plane should be
a solid area under the digital section of the device defined by pins 1 – 5 and 13 –16, plus associated
external components. The two ground planes should be connected together at a suitable point and
connected into the board ground.
The VSS connections to the Xtal oscillator capacitors C1 and C2 should also be low impedance and
preferably be part of the digital VSS ground plane to ensure reliable start up of the oscillator.
For best results, an Xtal oscillator design should drive the clock inverter input with signal levels of at least
40% of VDD peak-to-peak. To obtain Xtal oscillator design assistance, please consult your Xtal
manufacturer.
© 2007 CML Microsystems Plc
5
D/865A/3
5 Page 
Telecom Signalling Device
CMX865A
5.2. FSK Modulator
Serial data from the USART is fed to the FSK modulator if a V.21, V.23, Bell 103 or Bell 202 mode has
been selected.
The FSK modulator generates one of two frequencies according to the transmit mode and the value of the
current transmit data bit.
5.3. Tx Filter and Equaliser
The FSK modulator output signal is fed through the Transmit Filter which limits the out-of-band signal
energy to acceptable limits. In 1200bps modem modes this block includes a fixed compromise line
equaliser which is automatically set for the particular modulation type and frequency band being
employed. This fixed compromise line equaliser may be enabled or disabled by b10 of the General
Control Register. The amount of Tx equalisation provided compensates for one quarter of the relative
amplitude and delay distortion of ETS Test Line 1 over the frequency band used.
5.4. DTMF/Tone Generator
In DTMF/Tones mode this block generates DTMF signals (with programmable twist) or single or dual
frequency tones.
5.5. Tx Level Control and Output Buffer
The outputs (if present) of the Transmit Filter and DTMF/Tone Generator are passed through the
programmable Tx Level Control and Tx Output Buffer to the pins TXA and TXAN. The Tx Output Buffer
has symmetrical outputs to provide sufficient line voltage swing at low values of VDD and to reduce
harmonic distortion of the signal.
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© 2007 CML Microsystems Plc
11
D/865A/3
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CMX865A.PDF ] | |
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