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PDF NB7L32M Data sheet ( Hoja de datos )
| Número de pieza | NB7L32M | |
| Descripción | Clock Divider w/CML Output and Internal Termination | |
| Fabricantes | ON Semiconductor | |
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NB7L32M
2.5V/3.3V, 14GHz ÷2 Clock
Divider w/CML Output and
Internal Termination
Description
The NB7L32M is an integrated ÷2 divider with differential clock
inputs and asynchronous reset.
Differential clock inputs incorporate internal 50 W termination
resistors and accept LVPECL (Positive ECL), CML, or LVDS. The
high frequency reset pin is asserted on the rising edge. Upon
power−up, the internal flip−flops will attain a random state; the reset
allows for the synchronization of multiple NB7L32M’s in a system.
The differential 16 mA CML output provides matching internal
50 W termination which guarantees 400 mV output swing when
externally receiver terminated 50 W to VCC (See Figure 15).
The device is housed in a small 3x3 mm 16 pin QFN package.
Features
• Maximum Input Clock Frequency 14 GHz Typical
• 200 ps Max Propagation Delay
• 30 ps Typical Rise and Fall Times
• < 0.5 ps Maximum (RMS) Random Clock Jitter
• Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
• CML Output Level (400 mV Peak−to−Peak Output), Differential
Output Only
• 50 W Internal Input and Output Termination Resistors
• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
• These are Pb−Free Devices
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB7L
32M
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
FUNCTIONAL BLOCK DIAGRAM
R VCC
VTCLK
CLK
50 W
CLK
VTCLK
50 W
R1
Reset
VEE
Divide by 2
Q
Q
© Semiconductor Components Industries, LLC, 2011
January, 2011 − Rev. 3
TRUTH TABLE
CLK
CLK
R
Q
x x HL
Z W L ÷2
Z = LOW to HIGH Transition
W = HIGH to LOW Transition
x = Don’t Care
Q
H
÷2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
1 Publication Order Number:
NB7L32M/D
1 page  
NB7L32M
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.465 V, VEE = 0 V (Note 8)
−40°C
255C
Symbol
Characteristic
Min Typ Max Min Typ Max Min
VOUTPP
Output Voltage Amplitude (@ VINPP(MIN))
fin ≤ 7 GHz
(See Figures 2, 3, 4, 5, and 6)
fin ≤ 12 GHz
190 330
160 320
190 330
160 320
190
160
fIN Maximum Input Clock Frequency
(See Figure 2)
12 14
12 14
12
855C
Typ Max
330
320
14
Unit
mV
GHz
ttPPHLHL,
tskew
Propagation Delay to
Output Differential (See Figure 7)
Duty Cycle Skew (Note 9)
Device−to−Device Skew (Note 12)
CLK to Q 130 155 200 130 155 200 130 155 200 ps
R to Q 200 240 300 200 240 300 200 260 300
2 20
6 50
2 20
6 50
2 20
6 50
tRR Reset Recovery (See Figure 7)
300 135
300 135
300 135
ps
tPW Minimum Pulse Width
R 500 210
500 210
500 210
ps
tJITTER
Random Clock Jitter (RMS)
(Note 11)
ffiinn
≤
=
7 GHz
12 GHz
0.13 0.5
0.14 0.5
0.13 0.5
0.14 0.5
0.13 0.5 ps
0.14 0.5
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
150 2500 150 2500 150
2500 mV
tr Output Rise/Fall Times @ 1 GHz
tf (20% − 80%)
30 45
30 45
30 45 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured by forcing VINPP(MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps
(20% − 80%).
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ 1 GHz.
10. VINPP(MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode.
11. Additive RMS jitter with 50% duty cycle input clock signal.
12. Device−to−device skew is measured between outputs under identical transition @ 1 GHz.
450
400
350
300
250
200
150
100
50
0
0
2
VCC = 3.3 V
VCC = 2.5 V
4 6 8 10 12 14
INPUT CLOCK FREQUENCY (GHz)
Figure 2. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fOUT) at
Ambient Temperature (VINPP = 150 mV)
http://onsemi.com
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