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PDF MC33689 Data sheet ( Hoja de datos )
| Número de pieza | MC33689 | |
| Descripción | System Basis Chip | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC33689 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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MOTOROLA
Freescale
Semiconductor,
Inc.Order this document by
Rev: 2.71 Date: 15 Dec 2004
SEMICONDUCTOR
MC33689
TECHNICAL DATA
Product Preview
System Basis Chip with
LIN transceiver
LIN System basis chip
SILICON MONOLITHIC
INTEGRATED CIRCUIT
The LIN SBC is a monolithic integrated circuit combining many functions
frequently used by automotive LIN distributed slave nodes. It incorporates:
- Single voltage regulator with low power modes
- LIN physical interface.
- Wake up inputs.
- Triple high side driver
- Current sense op amp
• Vdd: Low drop voltage regulator, current limitation, over temperature
detection, monitoring and reset function, current capability 50mA.
• Programmable window watchdog
• Three operational modes (normal, stop and sleep modes)
• Low current consumption in sleep and stop modes
• LIN physical interface compatible with LIN standard.
• Two external high voltage wake-up inputs
• Dual high side switches, relay driver capability, internal clamp, PWM
capability.
• Single low current high side switch, 50mA capability for switch bias and hall
sensor supply
• Current sense amplifier
• Nominal DC operating voltage from 5.5 to 27V
• 40V maximum transient voltage
• Wake up capabilities (wake up inputs, LIN interface)
www.DataSheet4U.com
Pin out SO32WB fine pitch
NC 1
L1 2
NC 3
L2 4
HS3 5
HS2 6
HS1 7
T-GND 8
T-GND 9
VS2 10
LIN 11
GND 12
VS1 13
NC 14
Vdd 15
aGND 16
32 TX
31 RX
30 INT
29 CSB
28 MISO
27 MOSI
26 SCLK
25 T-GND
24 T-GND
23 IN
22 Reset
21 Wdc
20 e+
19 e-
18 Out
17 Vcc
Vbat
Simplified Block Diagram
Vs1
5V/50mA
Vdd
Voltage
Regulator
Reset
control
Reset
Vs2
HS1
HS2
HS3
L2
L1
LIN
Window
Watchdog
Wdc
pre driver
SPI and
Mode
Control
amplifier
IN
MOSI
MISO
SCK
CSB
INT
Vcc
E-
E+
Vs1
LIN Physical Interface
Gnd
aGnd
Out
TX
RX
ORDERING INFORMATION
Device
Operating
Temperature Range
MC33689DWB/R2 TA = -40 to 125°C
Package
SO-32
This document contains information on a product undeFr doevrelMopmoernet. MInotofroolramresaertvieos ntheOrignht This Product,
to change or discontinue this product without notice.
Go to: www.freescale.com
© Motorola,Inc 2004
1 page  
Freescale SMeCm33i6c89onductor, Inc.
(Vs1 and Vs2 from 5.5V to 18V and Tamb from -40°C to 125°C unless otherwise noted)
Description
Symbol
Characteristics
Min Typ Max
Reset pull down current
Reset Duration after Vdd High
Ipdw
1.5
8
reset-dur
0.65
1
1.35
Unit
mA
ms
IN: input
High Level Input Voltage
Vih 0.7Vdd
Vdd+0.3
V
Low Level Input Voltage
Vil -0.3
0.3Vdd
V
Input Current
Iin -10
10 µA
MISO: SPI output
Low Level Output Voltage
Vol 0
1.0 V
High Level Output Voltage
Voh Vdd-0.9
Vdd V
Tristated MISO Leakage Current
-2 +2 uA
MOSI, SCLK, CSB: SPI input
High Level Input Voltage
Vih 0.7Vdd
Vdd+0.3
Low Level Input Voltage
Vil -0.3
0.3Vdd
V
CSB Pull up current source
Iih -100
-20 uA
MOSI, SCK Input Current
Iin -10
10 uA
SPI: DIGITAL INTERFACE TIMING
SPI operation frequency
Freq
0.25
4 MHz
SCLK Clock Period
SCLK Clock High Time
SCLK Clock Low Time
Falling Edge of CS to Rising
Edge of SCLK
tpCLK
twSCLKH
twSCLKL
tlead
250
125
125
100
N/A ns
N/A ns
N/A ns
N/A ns
Falling Edge of SCLK to CS Rising Edge
tlag
100
N/A ns
MOSI to Falling Edge of SCLK
tSISU
40
N/A ns
Falling Edge of SCLK to MOSI
tSIH 40
N/A ns
MISO Rise Time (CL = 220pF)
trSO
25 50 ns
MISO Fall Time (CL = 220pF)
tfSO
25 50 ns
Time from Falling or Rising Edges of CS to:
- MISO Low Impedance
- MISO High Impedance
tSOEN
tSODIS
0
50 ns
50
Time from Rising Edge of SCLK to MISO
Data Valid
tvalid
0
50 ns
Conditions
Internally limited. Vdd<4V,
Vreset = 4.6V
0<VIN<Vdd
I out = 1.5mA
I out = -250uA
0V<Vmiso<Vdd
Vi 1V to 3.5V
0<VIN<Vdd
guaranteed by design
guaranteed by design
guaranteed by design
0.2 V1=<MISO>=0.8V1,
CL=100pF
guaranteed by design
MC33689
For More Information On This Product,
Go to: www.freescale.com
5
5 Page 
Freescale SMeC3m36i8c9onductor, Inc.
3 STATE MACHINE
Vddlow (150ms) expired and VSUV = 0
Vdd high & Reset counter (1ms) expired & W/D not selected
Reset
Vdd high & Reset counter (1ms)
expired & W/D selected
Vdd low OR (NR time
out occurs (150ms) &
W/D selected)
Normal
Request
Power
Down
Vdd low OR (W/D fail &
W/D selected)
Normal
Vdd low
Wake up
Stop
W/D selected means: external resistor between Wdc pin and gnd or Wdc pin open.
W/D not selected means Wdc pin connected to gnd.
W/D fail means: W/D trigger occurs in closed window or no SPI W/D trigger command.
Stop command means: SPI stop command.
Sleep command means: SPI sleep request followed by SPI sleep command.
Wake up means: L1 or L2 state change or LIN bus wake up or CSB rising edge.
Sleep
MC33689
For More Information On This Product,
Go to: www.freescale.com
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MC33689.PDF ] | |
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