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PDF MC74VHCT373A Data sheet ( Hoja de datos )
| Número de pieza | MC74VHCT373A | |
| Descripción | Octal D-Type Latch | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74VHCT373A
Octal D−Type Latch
with 3−State Output
The MC74VHCT373A is an advanced high speed CMOS octal latch
with 3−state output fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
This 8−bit D−type latch is controlled by a latch enable input and an
output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT373A input and output (when disabled) structures
provide protection when voltages between 0 V and 5.5 V are applied,
regardless of the supply voltage. These input and output structures
help prevent device destruction caused by supply
voltage−input/output voltage mismatch, battery backup, hot insertion,
etc.
Features
• High Speed: tPD = 7.7 ns (Typ) at VCC = 5.0 V
• Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°Cwww.DataSheet4U.com
• TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Designed for 4.5 V to 5.5 V Operating Range
• Low Noise: VOLP = 1.6 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
• Chip Complexity: 196 FETs or 49 Equivalent Gates
• Pb−Free Packages are Available*
http://onsemi.com
MARKING
DIAGRAMS
20
VHCT373A
1 SOIC−20WB
SUFFIX DW
AWLYYWWG
CASE 751D 1
20
1 TSSOP−20
SUFFIX DT
CASE 948E
1
VHCT
373A
ALYWG
G
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
INPUTS
OUTPUT
OE LE
D
Q
L HH
H
L HL
L
L L X No Change
HXX
Z
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 4
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Publication Order Number:
MC74VHCT373A/D
1 page  
MC74VHCT373A
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 7. Test Circuit
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 8. Test Circuit
D0
3
D
Q
D1
4
D
Q
D2
7
D
Q
D3
8
D
Q
D4
13
D
Q
D5
14
D
Q
D6
17
D
Q
D7
18
D
Q
11
LE
OE 1
LE LE LE LE LE LE LE LE
2 5 6 9 12 15 16 19
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Figure 9. Expanded Logic Diagram
http://onsemi.com
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC74VHCT373A.PDF ] | |
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