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PDF MC74VHCT259A Data sheet ( Hoja de datos )
| Número de pieza | MC74VHCT259A | |
| Descripción | 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter | |
| Fabricantes | ON Semiconductor | |
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MC74VHCT259A
8−Bit Addressable
Latch/1−of−8 Decoder
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHCT259 is an 8−bit Addressable Latch fabricated with
silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The VHC259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in
the mode selection table. In the addressable latch mode, the signal on
Data In is written into the addressed latch. The addressed latch follows
the data input with all non−addressed latches remaining in their
previous states. In the memory mode, all latches remain in their
previous state and are unaffected by the Data or Address inputs. In the
one−of−eight decoding or demultiplexing mode, the addressed output
follows the state of Data In with all other outputs in the LOW state. In
the Reset mode, all outputs are LOW and unaffected by the address
and data inputs. When operating the VHCT259 as an addressable
latch, changing more than one bit of the address cowuwwld.DatiamShepeto4Us.ceoma
transient wrong address. Therefore, this should only be done while in
the memory mode.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V because it
has full 5.0 V CMOS level output swings.
The VHCT259A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when VCC = 0 V. These
input and output structures help prevent device destruction caused by
supply voltage−input/output voltage mismatch, battery backup, hot
insertion, etc.
Features
• High Speed: tPD = 7.6 ns (Typ) at VCC = 5.0 V
• Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
• TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
• Power Down Protection Provided on Inputs and Outputs
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: HBM > 2000 V
• Pb−Free Packages are Available*
http://onsemi.com
MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
VHCT259AG
AWLYWW
11
16
TSSOP−16
VHCT
DT SUFFIX
259A
CASE 948F
ALYWG
G
11
16
SOEIAJ−16
M SUFFIX
CASE 966
74VHCT259
ALYWG
11
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
January, 2006 − Rev. 4
1
Publication Order Number:
MC74VHCT259A/D
1 page  
MC74VHCT259A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
VCC
TA = 25°C
TA ≤ 85°C −55°C ≤ TA ≤ 125°C
(V) Min Typ Max Min Max Min
Max Unit
VIH Minimum High−Level
Input Voltage
4.5 to 5.5 2
22
V
VIL Maximum Low−Level
Input Voltage
4.5 to 5.5
0.8 0.8
0.8 V
VOH Maximum High−Level VIN = VIH or VIL
Output Voltage
IOH = −50 mA
4.5 4.4 4.5
4.4
4.4
V
VIN = VIH or VIL
IOH = −8 mA
4.5 3.94
3.8 3.66
VOL Maximum Low−Level VIN = VIH or VIL
Output Voltage
IOL = 50 mA
4.5
0 0.1
0.1
V
0.1
VIN = VIH or VIL
IOH = 8 mA
4.5
0.36 0.44
0.52
IIN Input Leakage Current VIN = 5.5 V or GND 0 to 5.5
±0.1 ±1.0
±1.0 mA
ICC Maximum Quiescent VIN = VCC or GND
Supply Current
5.5
4.0 40.0
40.0 mA
ICCT
Additional Quiescent
Supply Current
(per Pin)
Any one input:
VIN = 3.4 V
All other inputs:
VIN = VCC or GND
5.5
1.35 1.5
1.5 mA
IOPD Output Leakage Current VOUT = 5.5 V
0
0.5 5
5 mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
tPHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCIN
Parameter
Maximum Propagation
Delay, Data to Output
(Figures 6 and 11)
Maximum Propagation
Delay, Address Select
to Output
(Figures 7 and 11)
Maximum Propagation
Delay, Enable to Output
(Figures 8 and 11)
Maximum Propagation
Delay, Reset to Output
(Figures 9 and 11)
Maximum Input
Capacitance
Test Conditions
VCC = 3.3 ± 0.3V CL = 15pF
CL = 50pF
VCC = 5.0 ± 0.5V CL = 15pF
CL = 50pF
VCC = 3.3 ± 0.3V CL = 15pF
CL = 50pF
VCC = 5.0 ± 0.5V CL = 15pF
CL = 50pF
VCC = 3.3 ± 0.3V CL = 15pF
CL = 50pF
VCC = 5.0 ± 0.5V CL = 15pF
CL = 50pF
VCC = 3.3 ± 0.3V CL = 15pF
CL = 50pF
VCC = 5.0 ± 0.5V CL = 15pF
CL = 50pF
TA = 25°C
Min Typ Max
8.5 11.0
8.5 16.0
6.0 8.0
6.0 10.0
8.5 11.0
8.5 16.0
6.0 8.0
8.5 10.0
8.5 11.0
8.5 16.0
6.0 8.0
8.5 10.0
8.5 11.0
8.5 16.0
6.0 8.0
8.5 10.0
6 10
TA = ≤ 85°C
Min Max
1.0 13.0
1.0 18.0
1.0 9.5
1.0 11.5
1.0 13.0
1.0 18.0
1.0 9.5
1.0 11.5
1.0 13.0
1.0 18.0
1.0 9.5
1.0 11.5
1.0 13.0
1.0 18.0
1.0 9.5
1.0 11.5
10
−55°C ≤ TA ≤ 125°C
Min Max
1.0 13.0
1.0 18.0
1.0 9.5
1.0 11.5
1.0 13.0
1.0 18.0
1.0 9.5
1.0 11.5
1.0 13.0
1.0 18.0
1.0 9.5
1.0 11.5
1.0 13.0
1.0 18.0
1.0 9.5
1.0 11.5
10
Unit
ns
ns
ns
ns
pF
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTypical @ 25°C, VCC = 5.0V
CPD Power Dissipation Capacitance (Note 5)
30 pF
5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
http://onsemi.com
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| PDF Descargar | [ Datasheet MC74VHCT259A.PDF ] | |
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