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PDF MC74VHC259 Data sheet ( Hoja de datos )
| Número de pieza | MC74VHC259 | |
| Descripción | 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter | |
| Fabricantes | ON Semiconductor | |
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MC74VHC259
8-Bit Addressable
Latch/1-of-8 Decoder
CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
The MC74VHC259 is an 8–bit Addressable Latch fabricated with
silicon gate CMOS technology. It achieves high speed operation similar to
equivalent Bipolar Schottky TTL devices while maintaining CMOS low
power dissipation.
The VHC259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in the
mode selection table.. In the addressable latch mode, the data on Data In
is written into the addressed latch. The addressed latch follows the data
input with all non–addressed latches remaining in their previous states. In
the memory mode, all latches remain in their previous state and are
unaffected by the Data or Address inputs. In the one–of–eight decoding
or demultiplexing mode, the addressed output follows the state of Data In
with all other outputs in the LOW state. In the Reset mode, all outputs are
LOW and unaffected by the address and data inputs. When operating the
VHC259 as an addressable latch, changing more than one bit of the
address could impose a transient wrong address. Therefore, this should
only be done while in the memory mode.
The MC74VHC259 input structure provides protectionwwwwh.DeantaSvheoetl4tUa.cgomes
up to 7 V are applied, regardless of the supply voltage. This allows the
MC74VHC259 to be used to interface 5 V circuits to 3 V circuits.
• High Speed: tPD = 7.6 ns (Typ) at VCC = 5 V
• Low Power Dissipation: ICC = 2 µA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• CMOS–Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: HBM > 2000 V
A0 1
A1 2
A2 3
Q0 4
Q1 5
Q2 6
Q3 7
GND 8
16 VCC
15 RESET
14 ENABLE
13 DATA IN
12 Q7
11 Q6
10 Q5
9 Q4
Figure 1. Pin Assignment
http://onsemi.com
MARKING DIAGRAMS
SOIC–16
D SUFFIX
CASE 751B
16 9
VHC259
AWLYYWW
18
TSSOP–16
DT SUFFIX
CASE 948F
SOIC EIAJ–16
M SUFFIX
CASE 966
16 9
VHC259
AWLYWW
1
8
16 9
VHC259
ALYW
18
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC74VHC259D
SOIC–16 48 Units/Rail
MC74VHC259DR2 SOIC–16 2500 Units/Reel
MC74VHC259DT TSSOP–16 96 Units/Rail
MC74VHC259DTR2 TSSOP–16 2500 Units/Reel
MC74VHC259M
SOIC
EIAJ–16
50 Units/Rail
SOIC
MC74VHC259MEL EIAJ–16 2000 Units/Reel
© Semiconductor Components Industries, LLC, 2001
April, 2001 – Rev. 2
1
Publication Order Number:
MC74VHC259/D
1 page  
MC74VHC259
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC
TA = 25°C
–55°C ≤ TA ≤ 125°C
Symbol
Parameter
Condition
(V) Min Typ Max Min Max Unit
VIH Minimum High–Level
Input Voltage
2.0 1.5
3.0to 5.5 VCCX 0.7
1.5
VCCX 0.7
V
VIL Maximum Low–Level
Input Voltage
2.0
3.0to 5.5
0.5
VCCX 0.3
0.5
VCCX 0.3
V
VOH
Maximum High–Level
VIN = VIH or VIL
2.0 1.9 2.0
1.9
V
Output Voltage
IOH = –50 µA
3.0 2.9 3.0
2.9
4.5 4.4 4.5
4.4
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA
3.0 2.58
4.5 3.94
V
2.48
3.8
VOL Maximum Low–Level VIN = VIH or VIL
Output Voltage
IOL = 50 µA
2.0
3.0
4.5
0.0 0.1
0.0 0.1
0.0 0.1
0.1 V
0.1
0.1
VIN = VIH or VIL
IOL = 4 mA
IOL = 8 mA
3.0
4.5
0.36
0.36
V
0.44
0.44
IIN
Input Leakage Current
VIN = 5.5 V or GND 0 to 5.5
±0.1 ±1.0 µA
ICC Maximum Quiescent VIN = VCC or GND
Supply Current
5.5
4.0 40.0 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Parameter
Maximum
Propagation Delay,
Data to Output
(Figures 6 and 11)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum
Propagation Delay,
Address Select to
Output
(Figures 7 and 11)
Maximum
Propagation Delay,
Enable to Output
(Figures 8 and 11)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Maximum
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay,
Reset to Output
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figures 9 and 11)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCIN MaximumInput
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCapacitance
Test Conditions
VCC = 3.3 ± 0.3V CL = 15pF
CL = 50pF
VCC = 5.0 ± 0.5V CL = 15pF
CL = 50pF
VCC = 3.3 ± 0.3V CL = 15pF
CL = 50pF
VCC = 5.0 ± 0.5V CL = 15pF
CL = 50pF
VCC = 3.3 ± 0.3V
VCC = 5.0 ± 0.5V
VCC = 3.3 ± 0.3V
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
TA = 25°C
Min Typ Max
6.0 8.5
8.5 12.5
4.9 8.0
7.0 10.0
6.0 8.5
8.5 12.5
4.9 8.0
7.0 10.0
6.0 8.5
8.5 12.5
4.9 8.0
7.0 10.0
6.0 8.5
8.5 12.5
4.9 8.0
7.0 10.0
6 10
TA ≤ 85°C
Min Max
1.0 11.5
1.0 14.5
1.0 9.5
1.0 11.5
1.0 11.5
1.0 14.5
1.0 9.5
1.0 11.5
1.0 11.5
1.0 14.5
1.0 9.5
1.0 11.5
1.0 11.5
1.0 14.5
1.0 9.5
1.0 11.5
10
–55°C ≤ TA ≤
125°C
Min Max
1.0 11.5
1.0 14.5
1.0 9.5
1.0 11.5
1.0 11.5
1.0 14.5
1.0 9.5
1.0 11.5
1.0 11.5
1.0 14.5
1.0 9.5
1.0 11.5
1.0 11.5
1.0 14.5
1.0 9.5
1.0 11.5
10
Unit
ns
ns
ns
ns
pF
Typical @ 25°C, VCC = 5.0V
CPD Power Dissipation Capacitance (Note 6.)
30 pF
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no–load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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| PDF Descargar | [ Datasheet MC74VHC259.PDF ] | |
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