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PDF AD9549 Data sheet ( Hoja de datos )
| Número de pieza | AD9549 | |
| Descripción | Dual Input Network Clock Generator/Synchronizer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Flexible reference inputs
Input frequencies: 8 kHz to 750 MHz
Two reference inputs
Loss of reference indicators
Auto and manual holdover modes
Auto and manual switchover modes
Smooth A-to-B phase transition on outputs
Excellent stability in holdover mode
Programmable 16 + 1-bit input divider, R
Differential HSTL clock output
Output frequencies to 750 MHz
Low jitter clock doubler for frequencies of >400 MHz
Single-ended CMOS output for frequencies of <150 MHz
Programmable digital loop filter (<1 Hz to ~100 kHz)
High speed digitally controlled oscillator (DCO) core
Direct digital synthesizer (DDS) with integrated 14-bit DAC
Excellent dynamic performance
Programmable 16 + 1-bit feedback divider, S
Software controlled power-down
Available 64-lead LFCSP package
Dual Input Network Clock
Generator/Synchronizer
AD9549
APPLICATIONS
Network synchronization
Reference clock jitter cleanup
SONET/SDH clocks up to OC-192, including FEC
Stratum 3/3E reference clocks
Wireless base station, controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9549 provides synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9549 generates an output clock, synchronized to one of two
external input references. The external references may contain
significant time jitter, also specified as phase noise. Using a
digitally controlled loop and holdover circuitry, the AD9549
continues to generate a clean (low jitter), valid output clock during
a loss of reference condition, even when both references have failed.
The AD9549 operates over an industrial temperature range of
−40°C to +85°C.
AD9549
BASIC BLOCK DIAGRAM
FDBK_IN
S1 TO S4
REFA_IN
REFB_IN
REFERENCE
MONITORS
AND
SWITCHING
R
DIGITAL PLL
R, S DIVIDERS
HOLDOVER
DAC_OUT
FILTER
CLOCK
OUTPUT
DRIVERS
OUT
OUT_CMOS
SERIAL PORT,
I/O LOGIC
SYSTEM CLOCK
MULTIPLIER
DIGITAL INTERFACE
Figure 1.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
1 page  
AD9549
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V ± 5%, AVDD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%. AVSS = 0 V, DVSS = 0 V, unless otherwise noted.
Table 1.
Parameter
SUPPLY VOLTAGE
DVDD_I/O (Pin 1)
DVDD (Pin 3, Pin 5, Pin 7)
AVDD3 (Pin 14, Pin 46, Pin 47, Pin 49)
AVDD3 (Pin 37)
AVDD (Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29,
Pin 30, Pin 36, Pin 42, Pin 44, Pin 45, Pin 53)
SUPPLY CURRENT
IAVDD3 (Pin 14)
IAVDD3 (Pin 37)
IAVDD3 (Pin 46, Pin 47, Pin 49)
IAVDD (Pin 36, Pin 42)
Min
3.135
1.71
3.135
1.71
1.71
IAVDD (Pin 11)
IAVDD (Pin 19, Pin 23 to Pin 26, Pin 29,
Pin 30, Pin 44, Pin 45)
IAVDD (Pin 53)
IDVDD (Pin 3, Pin 5, Pin 7)
IDVDD_I/O (Pin 1)
LOGIC INPUTS (Except Pin 32)
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IINH, IINL)
Maximum Input Capacitance (CIN)
CLKMODESEL (Pin 32) LOGIC INPUT
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IINH, IINL)
Maximum Input Capacitance (CIN)
LOGIC OUTPUTS
2.0
DVSS
1.4
AVSS
Typ
3.30
1.80
3.30
3.30
1.80
4.7
3.8
26
21
12
215
41
254
4
±60
3
−18
3
Max
3.465
1.89
3.465
3.465
1.89
5.6
4.5
29
26
15
281
49
265
6
DVDD_I/O
0.8
±200
AVDD
0.4
−50
Output High Voltage (VOH)
Output Low Voltage (VOL)
REFERENCE INPUTS
Input Capacitance
Input Resistance
Differential Operation
Common Mode Input Voltage1
(Applicable When DC-Coupled)
Differential Input Voltage Swing1
Single-Ended Operation
Input Voltage High (VIH)
Input Voltage Low (VIL)
Threshold Voltage
Input Current
FDBK_IN INPUT
Input Capacitance
Input Resistance
Differential Input Voltage Swing2
2.7
DVSS
DVDD_I/O
0.4
3
8.5 11.5 14.5
1.5 AVDD3 −
0.2
500
2.0
AVSS
AVDD3 −
0.66
AVDD3 −
0.82
AVDD3
0.8
AVDD3 −
0.98
1
3
18 22
225
26
Unit
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
µA
pF
V
V
µA
pF
V
V
pF
kΩ
V
mV p-p
V
V
V
mA
pF
kΩ
mV p-p
Test Conditions/Comments
Pin 37 is typically 3.3 V, but can be set to 1.8 V
REFA, REFB buffers
CMOS output clock driver at 3.3 V
DAC output current source, fS = 1 GSPS
FDBK_IN input, HSTL output clock driver
(output doubler turned on)
REFA and REFB input buffer 1.8 V supply
Aggregate analog supply, including system
clock PLL
DAC power supply
Digital core
Digital I/O (varies dynamically)
Pin 9, Pin 10, Pin 54 to Pin 61, Pin 63, Pin 64
At VIN = 0 V and VIN = DVDD_I/O
Pin 32 only
At VIN = 0 V and VIN = AVDD
Pin 62 and the following bidirectional pins:
Pin 9, Pin 10, Pin 54, Pin 55, Pin 63
IOH = 1 mA
IOL = 1 mA
Pin 12, Pin 13, Pin 15, Pin 16
Differential at Register 0x040F[1:0] = 00
Differential operation; note that LVDS signals
must be ac-coupled
Differential operation
Register 0x040F[1:0] = 10
Register 0x040F[1:0] = 10 (other settings
possible)
Single-ended operation
Pin 40, Pin 41
Differential
−12 dBm into 50 Ω; must be ac-coupled
Rev. D | Page 4 of 76
5 Page 
AD9549
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DVDD_I/O 1
DVSS 2
DVDD 3
DVSS 4
DVDD 5
DVSS 6
DVDD 7
DVSS 8
S1 9
S2 10
AVDD 11
REFA_IN 12
REFA_INB 13
AVDD3 14
REFB_IN 15
REFB_INB 16
PIN 1
INDICATOR
AD9549
TOP VIEW
(Not to Scale)
48 DAC_RSET
47 AVDD3
46 AVDD3
45 AVDD
44 AVDD
43 AVSS
42 AVDD
41 FDBK_IN
40 FDBK_INB
39 AVSS
38 OUT_CMOS
37 AVDD3
36 AVDD
35 OUT
34 OUTB
33 AVSS
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED THERMAL DIE ON THE BOTTOM OF THE PACKAGE PROVIDES
THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Input/
Output Pin Type
1 I Power
2, 4, 6, 8
I
Power
3, 5, 7
I Power
9, 10, 54, 55 I/O
3.3 V CMOS
11, 19, 23 to
26, 29, 30, 36,
42, 44, 45, 53
12
I
I
Power
Differential
input
13 I
14, 46, 47, 49 I
15 I
Differential
input
Power
Differential
input
16
17, 18
I Differential
input
Mnemonic
DVDD_I/O
DVSS
DVDD
S1, S2, S3, S4
AVDD
REFA_IN
REFA_INB
AVDD3
REFB_IN
REFB_INB
NC
Description
I/O Digital Supply.
Digital Ground. Connect to ground.
Digital Supply.
Configurable I/O Pins. These pins are configured under program control (see
the Status and Warnings section) and do not have internal pull-up/pull-down
resistors.
Analog Supply. Connect to a nominal 1.8 V supply.
Frequency/Phase Reference A Input. This internally biased input is typically
ac-coupled and, when configured as such, can accept any differential signal
with single-ended swing between 0.4 V and 3.3 V. If dc-coupled, LVPECL or
CMOS input is preferred.
Complementary Frequency/Phase Reference A Input. Complementary signal
to the input provided on Pin 12. If using a single-ended, dc-coupled CMOS
signal into REFA_IN, bypass this pin to ground with a 0.01 μF capacitor.
Analog Supply. Connect to a nominal 3.3 V supply.
Frequency/Phase Reference B Input. This internally biased input is typically
ac-coupled and, when configured as such, can accept any differential signal
with single-ended swing between 0.4 V and 3.3 V. If dc-coupled, LVPECL or
CMOS input is preferred.
Complementary Frequency/Phase Reference B Input. Complementary signal
to the input provided on Pin 15. If using a single-ended, dc-coupled CMOS
signal into REFB_IN, bypass this pin to ground with a 0.01 μF capacitor.
No Connect. These are excess, unused pins that can be left floating.
Rev. D | Page 10 of 76
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9549.PDF ] | |
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