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PDF MC74LVX74 Data sheet ( Hoja de datos )
| Número de pieza | MC74LVX74 | |
| Descripción | Dual D-Type Flip-Flop | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual D-Type Flip-Flop
with Set and Clear
With 5V-Tolerant Inputs
The MC74LVX74 is an advanced high speed CMOS D–type flip–flop.
The inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
The signal level applied to the D input is transferred to O output during
the positive going transition of the Clock pulse.
Clear (CD) and Set (SD) are independent of the Clock (CP) and are
accomplished by setting the appropriate input Low.
• High Speed: fmax = 145MHz (Typ) at VCC = 3.3V
• Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Low Noise: VOLP = 0.5V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
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VCC CD2 D2 CP2 SD2 O2 O2
14 13 12 11 10 9 8
MC74LVX74
LVX
LOW–VOLTAGE CMOS
D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
DT SUFFIX
14–LEAD TSSOP PACKAGE
CASE 948G–01
1234567
CD1 D1 CP1 SD1 O1 O1 GND
Figure 1. 14–Lead Pinout (Top View)
M SUFFIX
14–LEAD SOIC EIAJ PACKAGE
CASE 965–01
PIN NAMES
Pins
Function
CP1, CP2
D1, D2
CD1, CD2
SD1, SD2
On, On
Clock Pulse Inputs
Data Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
6/97
© Motorola, Inc. 1997
DataSheet4 U .com
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CP 50%
50% VCC
O or O
tw
1/fmax
tPLH
tPHL
Figure 3.
D
CP
SWITCHING WAVEFORMS
SD or CD
tw
50%
VCC tPHL
GND
O or O
50% VCC
tPLH
O or O
50% VCC
trec
CP 50%
VALID
50%
tsu th
50%
Figure 5.
Figure 4.
VCC
GND
VCC
GND
MC74LVX74
VCC
GND
VCC
GND
TEST CIRCUIT
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 6.
LCX DATA
DataSheetB4RU13.c39om— REV 3
5
MOTOROLA
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC74LVX74.PDF ] | |
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