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PDF MT91L61 Data sheet ( Hoja de datos )
| Número de pieza | MT91L61 | |
| Descripción | (MT91L60 / MT91L61) 3 Volt Multi-Featured Codec | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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ISO2-CMOS MT91L60/61
3 Volt Multi-Featured Codec (MFC)
Data Sheet
Features
• Single 2.7-3.6 volt supply operation
• MT91L61 version features a delayed framing
pulse in SSI and ST-BUS modes to facilitate
cascaded devices
• Programmable µ-Law/A-Law Codec and Filters
• Programmable ITU-T (G.711)/sign-magnitude
coding
• Programmable transmit, receive and side-tone
gains
• Fully differential interface to handset transducers
- including 300 ohm receiver driver
• Flexible digital interface including ST-BUS/SSI
• Serial microport
• Low power operation
• ITU-T G.714 compliant
• Multiple power down modes
March 2006
Ordering Information
MT91L61AE
24 Pin PDIP
MT91L60AE
24 Pin PDIP
MT91L61AS 24 Pin SOIC
MT91L60AS 20 Pin SOIC
MT91L61AN
24 Pin SSOP
MT91L60AN 20 Pin SSOP
MT91L60ASR 20 Pin SOIC
MT91L61ASR 24 Pin SOIC
MT91L61ASR1 24 Pin SOIC*
MT9160AN1 20 Pin SSOP*
*Pb Free Matte Tin
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tape & Reel
Tape & Reel
Tape & Reel
Tubes
-40°C to +85°C
Applications
• Battery operated equipment
• Digital telephone sets
• Cellular radio sets
• Local area communications stations
• Pair Gain Systems
• Line cards
VSSD
VDD
VSSA
VBias
VRef
FILTER/CODEC GAIN
ENCODER 7dB
DECODER -7dB
Transducer
Interface
Din
Dout
STB/F0i
CLOCKin
STBd/FOod
(MT91L61only)
Flexible
Digital
Interface
Timing
ST-BUS
C&D
Channels
Serial Microport
PWRST IC
CS DATA1 DATA2 SCLK
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved.
M-
M+
HSPKR +
HSPKR -
A/µ/IRQ
1 page  
MT91L60/61
Data Sheet
Functional Description
Filter/Codec
The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain
compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are
programmable. These are ITU-T G.711 A-law or µ-Law, with true-sign/Alternate Digit Inversion or true-sign/Inverted
Magnitude coding, respectively. Optionally, sign-magnitude coding may also be selected for proprietary
applications.
The Filter/Codec block also implements transmit and receive audio path gains in the analog domain. A
programmable gain, voice side-tone path is also included to provide proportional transmit speech feedback to the
handset receiver. This side tone path feature is disabled by default. Figure 3 depicts the nominal half-channel and
side-tone gains for the MT91L60/61.
In the event of PWRST, the MT91L60/61 defaults such that the side-tone path is off, all programmable gains are set
to 0dB and ITU-T µ-Law is selected. Further, the digital port is set to SSI mode operation at 2048 kb/s and the FDI
and driver sections are powered up. (See Microport section.)
The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide
dynamic range from a single 3 volt supply design. This fully differential architecture is continued into the Transducer
Interface section to provide full chip realization of these capabilities for the handset functions.
A reference voltage (VRef), for the conversion requirements of the Codec section, and a bias voltage (VBias), for
biasing the internal analog sections, are both generated on-chip. VBias is also brought to an external pin so that it
may be used for biasing external gain setting amplifiers. A 0.1µF capacitor must be connected from VBias to analog
ground at all times. Although VRef may only be used internally, a 0.1µF capacitor must be connected from VRef to
ground. The analog ground reference point for these two capacitors must be physically the same point. To facilitate
this the VRef and VBias pins are situated on adjacent pins.
The transmit filter is designed to meet ITU-T G.714 specifications. The nominal gain for this filter is 0 dB (gain
control = 0 dB). Gain control allows the output signal to be increased up to 7 dB. An anti-aliasing filter is included.
This is a second order lowpass implementation with a corner frequency at 25 kHz.
The receive filter is designed to meet ITU-T G.714 specifications. The nominal gain for this filter is 0 dB (gain control
= 0 dB). Gain control allows the output signal to be attenuated up to 7 dB. Filter response is peaked to compensate
for the sinx/x attenuation caused by the 8 kHz sampling rate.
Side-tone is derived from the input of the Tx filter and is not subject to the gain control of the Tx filter section. Side-
tone is summed into the receive handset transducer driver path after the Rx filter gain control section so that Rx
gain adjustment will not affect side-tone levels. The side-tone path may be enabled/disabled with the gain control
bits located in Gain Control Register 2 (address 01h).
Transmit and receive filter gains are controlled by the TxFG0-TxFG2 and RxFG0-RxFG2 control bits, respectively.
These are located in Gain Control Register 1 (address 00h). Transmit filter gain is adjustable from 0dB to +7dB and
receive filter gain from 0dB to -7dB, both in 1dB increments.
Side-tone filter gain is controlled by the STG0-STG2 control bits located in Gain Control Register 2 (address 01h).
Side-tone gain is adjustable from -9.96 dB to +9.96 dB in 3.32 dB increments.
Companding law selection for the Filter/Codec is provided by the A/µ companding control bit while the coding
scheme is controlled by the Smag/ITU-T control bit. The A/µ control bit is logically OR’ed with the A/µ pin providing
access in both controller and controllerless modes. Both A/µ and Smag/ITU-T reside in Control Register 2 (address
04h). Table 1 illustrates these choices.
5
Zarlink Semiconductor Inc.
5 Page 
MT91L60/61
Data Sheet
When CEN is high, data written to the C-Channel register (address 05h) is transmitted, most significant bit first, on
DSTo. On power-up reset (PWRST) or software reset (Rst, address 03h) all C-Channel bits default to logic high.
Receive C-Channel data (DSTi) is always routed to the read register regardless of this control bit's logic state.
When low, data transmission is halted and this timeslot is tri-stated on DSTo.
B1-Channel and B2-Channel
Channels 2 and 3 are the B1 and B2 channels, respectively. B-channel PCM associated with the Filter/Codec and
transducer audio paths is selected on an independent basis for the transmit and receive paths. TxBSel and RxBSel
(Control Register 1, address 03h) are used for this purpose.
If no valid transmit path has been selected then the timeslot output on DSTo is tri-stated (see PDFDI and PDDR
control bits, Control Register 1 address 03h).
IRQ
Microport Read/Write Access
FP
n-3 n-2 n-1 n
n+1 n+2 n+3 n+4*
DSTo/
DSTi
Di-bit Group
Receive
D-Channel
I
D0
II III IV
D1 D2
D3 D4
D5 D6
D7
No preset value
Di-bit Group
I
Transmit D0
D-Channel
II III IV
D1 D2
D3 D4
D5 D6
D7
Power-up reset to 1111 1111
* note that frame n+4 is equivalent to frame n of the next cycle.
Figure 7a - D-Channel 16 kb/s Operation
FP
C4i
C2
DSTo/
DSTi
IRQ
D0
8 kb/s operation
D1
tif =500 nsec max
16 kb/s operation
Microport Read/Write Access
Figure 7b - IRQ Timing Diagram
tir =500 nsec max
Rpullup= 10 k
Reset coincident with
Read/Write of Address 04 Hex
or next FP, whichever occurs first
11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 33 Páginas | |
| PDF Descargar | [ Datasheet MT91L61.PDF ] | |
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