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PDF MCR8DSM Data sheet ( Hoja de datos )

Número de pieza MCR8DSM
Descripción Sensitive Gate Silicon Controlled Rectifiers Reverse Blocking Thyristors
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MCR8DSM, MCR8DSN
Preferred Device
Sensitive Gate
Silicon Controlled Rectifiers
Reverse Blocking Thyristors
Designed for high volume, low cost, industrial and consumer
applications such as motor control; process control; temperature, light
and speed control.
Features
Small Size
Passivated Die for Reliability and Uniformity
Low Level Triggering and Holding Characteristics
Available in Two Package Styles
Surface Mount Lead Form − Case 369C
Miniature Plastic Package − Straight Leads − Case 369
Epoxy Meets UL 94 V−0 @ 0.125 in
ESD Ratings: Human Body Model, 3B u 8000 V
Machine Model, C u 400 V
Pb−Free Packages are Available
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Peak Repetitive Off−State Voltage (Note 1)
(TJ = −40 to 110°C, Sine Wave, 50 to 60 Hz,
Gate Open)
MCR8DSM
MCR8DSN
VDRM,
VRRM
600
800
V
On−State RMS Current
(180° Conduction Angles; TC = 90°C)
IT(RMS)
8.0
A
Average On−State Current
(180° Conduction Angles; TC = 90°C)
Peak Non-Repetitive Surge Current
(1/2 Cycle, Sine Wave 60 Hz, TJ = 110°C)
Circuit Fusing Consideration (t = 8.3 msec)
IT(AV)
ITSM
I2t
5.1 A
90 A
34 A2sec
Forward Peak Gate Power
(Pulse Width 1.0 msec, TC = 90°C)
PGM 5.0 W
Forward Average Gate Power
(t = 8.3 msec, TC = 90°C)
PG(AV)
0.5
W
Forward Peak Gate Current
(Pulse Width 1.0 msec, TC = 90°C)
IGM 2.0 A
Operating Junction Temperature Range
TJ −40 to 110 °C
Storage Temperature Range
Tstg −40 to 150 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. VDRM and VRRM for all types can be applied on a continuous basis. Ratings
apply for negative gate voltage; positive gate voltage shall not be applied
concurrent with negative potential on the anode. Blocking voltages shall not
be tested with a constant current source such that the voltage ratings of the
device are exceeded.
http://onsemi.com
SCRs
8 AMPERES RMS
600 − 800 VOLTS
G
AK
MARKING
DIAGRAM
4
DPAK
CASE 369C
1 STYLE 4
YWW
CR
8DSxG
Y=
WW =
CR8DSx =
G=
Year
Work Week
Device Code
x= M or N
Pb−Free Package
PIN ASSIGNMENT
1 Cathode
2 Anode
3 Gate
4 Anode
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 4
1
Publication Order Number:
MCR8DSM/D

1 page




MCR8DSM pdf
MCR8DSM, MCR8DSN
10
TJ = 25°C
8.0
6.0
IGT = 25 mA
4.0
2.0 IGT = 10 mA
0
100
1000
RGK, GATE−CATHODE RESISTANCE (OHMS)
Figure 9. Holding Current versus
Gate−Cathode Resistance
10 K
1000
100 70°C
90°C
TJ = 110°C
10
1.0
100
RGK, GATE−CATHODE RESISTANCE (OHMS)
1000
Figure 10. Exponential Static dv/dt versus
Gate−Cathode Resistance and Junction
Temperature
1000
400 V
100 600 V
VPK = 800 V
10
TJ = 110°C
1000
100 IGT = 25 mA
IGT = 10 mA
10
VD = 800 V
TJ = 110°C
1.0
100
RGK, GATE−CATHODE RESISTANCE (OHMS)
1000
Figure 11. Exponential Static dv/dt versus
Gate−Cathode Resistance and Peak Voltage
1.0
100
RGK, GATE−CATHODE RESISTANCE (OHMS)
1000
Figure 12. Exponential Static dv/dt versus
Gate−Cathode Resistance and Gate Trigger
Current Sensitivity
http://onsemi.com
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