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PDF PI90LVB16 Data sheet ( Hoja de datos )
| Número de pieza | PI90LVB16 | |
| Descripción | 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver | |
| Fabricantes | Pericom Semiconductor | |
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PI90LVB161122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
Features
General Description
Master/Slave clock selection in a backplane application
160 MHz operation (typical)
100ps duty cycle distortion (typical)
50ps channel to channel skew (typical)
3.3V power supply design
Glitch-free power on at CLKI/O pins
Low Power design (16mA @ 3.3V static)
Accepts small swing (300mV typical) differential signal levels
Industrial temperature operating range (40°C to +85°C)
Available in 24-pin TSSOP Packaging (L)
PI90LVB16 is a six-channel LVTTL clock distribution driver with 50
picosecond channel-to-channel skew. It translates one BLVDS
(Bus Low-Voltage Differential Signaling) input signal into six LVTTL-
compatible output signals for distribution to adjacent chips on the
same board. The PI90LVB16 accepts BLVDS (300mV typical) differ-
ential input levels, and translates them to 3V CMOS output levels.
The 160MHz PI90LVB16 can be the master clock, driving inputs of
other clock I/O pins in a multipoint environment. It can also drive
the BLVDS backplane with a separate channel acting as a return/
source LVTTL clock source. The master/slave clock selection of the
driving source is controlled by the CrdCLKIN and the DE pins. An
output enable pin OE, when high, forces all CLKOUT pins high.
A backplane clock distribution network must be able to drive many
transmission line stubs. The Bus LVDS feature of the PI90LVB16 is
ideal for driving data transfers in large, high-performance backplane
system applications. The device can be used as a source synchro-
nous driver to distribute clock signals within data and telecommu-
nications systems.
Driver Mode Truth Table
Input
OE DE CrdCLKIN CLKI/O+
LL
L
L
LL
H
H
HL
L
L
HL
H
H
HH
X
Z
Output
CLKI/O
H
L
H
L
Z
CLKOUT
L
H
H
H
H
Receive Mode Truth Table
Input
Output
OE DE CrdCLKIN (CLKI/O+)(CLKI/O) CLKOUT
HH
X
XH
LH
X
VID ≥ 0.07V
H
LH
X
VID ≤ 0.07V
L
L = Low Logic State; H = High Logic State; X = Irrelevant
Z = High Impedance
Function Diagram
OE
CLKI/0+
CLKI/0–
R
D
Delay
MUX
CLKOUT0
CLKOUT1
CLKOUT5
DE
CrdCLKIN
1 PS8536A 05/21/01
1 page  
PI90LVB16
3V Bus LVDS 1-to-6
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DC Electrical Characteristics (continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specificed(3,4)
Symbol
Parameter
Conditions
VOD
Driver Output Differential
Voltage
∆VOD
VOS
∆VOS
Driver VOD Magnitude
Change
Driver Offset Voltage
Driver Offset Voltage
Multitude Change
RL = 37.5Ω, Figure 5
DE = 0V
Pin Min. Typ. Max. Units
250 350 450
mV
2 20
1.1 1.25 1.5 V
1 20 mV
VOHD Driver Output High
1.4 1.8
VOLD
IOS1D
Driver Output Low
Driver Differential Short
Circuit Current(6)
CLKI/O+, 0.8 1.05
CLKI/O
CrdCLKIN = VCC or GND,
VOD = 0V, (outputs shorted together), DE = 0V
±13 ±17
IOS2D
IOS3D
Driver Differential Short
Circuit Current to VCC(6)
CrdCLKIN = GND, DE = 0V, CLKI/O+ = VCC
CrdCLKIN = VCC, DE = 0V, CLKI/O = VCC
11 17
10 17
IOS4D
IOS5D
Driver Differential Short CrdCLKIN = VCC, DE = 0V, CLKI/O+ = 0V
Circuit Current to GND(6) CrdCLKIN = GND, DE = 0V, CLKI/O = 0V
15 17
15 17
IOFF
Power Off Leakage
Current
VCC = 0V or Open, VAPPLIED = 3.6V
±20
V
mA
µA
Switching Characteristics
Differential Receiver Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specificed(7,8)
Symbol
Parameter
Conditions
tPHLDR Differential Propagation Delay High to Low. CLKI/O to CLKOUT
tPLHDR
tSK1R
tSK2R
tSK3R
tTLHR
tTHLR
tPLHOER
tPHLOER
fMAX
Differential Propagation Delay Low to High. CLKI/O to CLKOUT
Duty Cycle Distortion(10) pulse skew, tPLH tPHL
Channel-to-Channel Skew; Same Edge(11)
Part-to-Part Skew(12)
Transition Time Low-to-High(9), (20% to 80%)
Transition Time High-to-Low(9), (80% to 20%)
Propagation Delay Low-to-High (OE to CLKOUT)
Propagation Delay High-to-Low (OE to CLKOUT)
Maximum Operating Frequency(15)
CL = 15pF
VID = 250mV
Figures 1 & 2
CL = 15pF
Figures 3 & 4
Min.
1.3
1.3
1.0
1.0
1.0
1.0
100
Typ.(1)
2.6
2.6
5
5
1.4
1.3
2.1
2.1
160
Max.
3.8
3.8
400
80
TBD
2.4
2.4
3.2
3.2
Units
ns
ps
ns
MHz
5 PS8536A 05/21/01
5 Page 
PI90LVB16
3V Bus LVDS 1-to-6
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Parameter Measurement Information
VCC
0V
CrdCLKIN D
Pulse DE
Generator
509
CL
CL
RL/2
1.2V
RL/2
Figure 10. Driver 3-State Test Circuit
DE 50%
CLKI/O+ (CrdCLKIN - L)
CLKI/O– (CrdCLKIN - H)
CLKI/O+ (CrdCLKIN -H)
CLKI/O– (CrdCLKIN - L)
tPLZD
50%
tPHZD
50%
tPZLD
50%
tPZhD
50%
VCC
0V
1.2V
VOL
VOH
1.2V
Figure 11. Driver 3-State Waveforms
1 1 PS8536A 05/21/01
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet PI90LVB16.PDF ] | |
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