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PDF MAX3353E Data sheet ( Hoja de datos )
| Número de pieza | MAX3353E | |
| Descripción | USB On-the-Go Charge Pump | |
| Fabricantes | Maxim Integrated Products | |
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19-2845; Rev 1; 10/03
USB On-the-Go Charge Pump with Switchable
Pullup/Pulldown Resistors
General Description
The MAX3353E I2C™-compatible USB On-The-Go
(OTG) regulated charge pump with switchable
pullup/pulldown resistors allows peripherals and mobile
devices such as PDAs, cellular phones, and digital
cameras to be interconnected without a host PC.
The MAX3353E enables a system with an integrated
USB dual-role transceiver to function as a USB OTG
dual-role device. The charge pump in the MAX3353E
supplies VBUS power and signaling that is required by
the transceiver as defined in On-The-Go Supplement:
USB 2.0, Revision 1.0. The MAX3353E provides the
switchable pullup and pulldown resistors on D+ and D-
required for a dual-role device.
The MAX3353E integrates a regulated charge pump,
switchable pullup/pulldown resistors, and an I2C-com-
patible 2-wire serial interface. The device provides a
detector to monitor ID status and operates with logic
supply voltages (VL) between +1.65V and VCC and
charge-pump supply voltages (VCC) from +2.6V to
+5.5V. The charge pump supplies an OTG-compatible
output on VBUS while sourcing 8mA output current.
The MAX3353E enables USB OTG communication
between digital logic parts that cannot supply or tolerate
the +5V VBUS levels that USB OTG requires. By control-
ling and measuring VBUS using internal comparators,
this device supports USB OTG session request protocol
(SRP) and host negotiation protocol (HNP).
The MAX3353E has built-in ±15kV ESD protection circuitry
to guard VBUS, ID_IN, D+, and D-. The MAX3353E is
available in a 5 x 4 chip-scale package (UCSP™) and
16-pin TSSOP package.
Applications
Mobile Phones
PDAs
Digital Cameras
MP3 Players
Photo Printers
Pin Configurations appear at end of data sheet.
Typical Applications Circuit appears at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
Purchase of I2C components from Maxim Integrated Products,
Inc., or one of its sublicensed Associated Companies, conveys
a license under the Philips I2C Patent Rights to use these com-
ponents in an I2C system, provided that the system conforms
to the I2C Standard Specification as defined by Philips.
Features
o Ideal for Enabling USB Dual-Role Components for
USB OTG Protocol
o Charge Pump for VBUS Signaling and Operation
Down to +2.6V
o Level Translators Allow Low-Voltage System
Interface
o Internal VBUS Comparators and ID Detector
o Internal Switchable Pullup and Pulldown
Resistors for Host/Peripheral Functionality
o I2C-Compatible Bus Interface with Command and
Status Registers
o Interrupt Features
o ±15kV ESD Protection on ID_IN, VBUS, D+, and D-
o Supports SRP and HNP
o Available in 5 x 4 UCSP and 16-Pin TSSOP
Ordering Information
PART
MAX3353EEUE
MAX3353EEBP-T
TEMP RANGE
PIN-
PACKAGE
-40°C to +85°C 16 TSSOP
-40°C to +85°C 5 x 4 UCSP
PKG
CODE
—
B20-4
Functional Diagram
VCC
ID_OUT
VL
C+ C-
VBUS
COMPARATORS
CHARGE
PUMP
CURRENT
GENERATOR
200kΩ
ID DETECTOR
±15kV
ESD
PROTECTION
VBUS
ID_IN
D+
SCL
SDA
INT
ADD
110kΩ
SE0
DRIVER
PULLUP/DOWN
RESISTORS
MAX3353E
D-
VTRM
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
USB On-the-Go Charge Pump with Switchable
Pullup/Pulldown Resistors
TIMING CHARACTERISTICS (continued)
(VCC = +2.6V to +5.5V, VL = +1.65V to VCC, VTRM = +3V to +3.6V, CFLYING = 0.1µF, VCC decoupled with 1µF capacitor to ground.
VTRM and VL decoupled with 0.1µF capacitor to ground. CVBUS = 1µF (min), TA = TMIN to TMAX, unless otherwise noted. Typical val-
ues are at TA = +25°C, VCC = +4V, VL = +1.8V, VTRM = +3.3V.) (Notes 3, 4)
PARAMETER
SYMBOL
CONDITION
MIN TYP MAX UNITS
INT Out Fall Time
CLOAD = 50pF
20 ns
ID_OUT Rise Time
ID_OUT Fall Time
CLOAD = 50pF
CLOAD = 50pF
30 ns
10 ns
Time to Exit Shutdown
500 µs
Time to Enter Shutdown
1000
µs
I2C/SMBUS-COMPATIBLE TIMING SPECIFICATIONS
(VCC = +2.6V to +5.5V, VL = +1.65V to VCC, VTRM = +3V to +3.6V, CFLYING = 0.1µF, VCC decoupled with 1µF capacitor to ground.
VTRM and VL decoupled with 0.1µF capacitor to ground. CVBUS = 1µF (min). TA = TMIN to TMAX, unless otherwise noted. Typical val-
ues are at VCC = +4V, VL = +1.8V, VTRM = +3.3V, and TA = +25°C.) (Notes 3, 4)
PARAMETER
SYMBOL
CONDITION
MIN TYP MAX UNITS
Serial Clock Frequency
fSCL
DC 400 kHz
Bus Free Time Between Stop and
Start Conditions
tBUF
1.3 µs
Start Condition Hold Time
Stop Condition Setup Time
Clock Low Period
Clock High Period
Data Setup Time
Data Hold Time
tHD:STA
tSU:STO
tLOW
tHIGH
tSU:DAT
tHD:DAT
(Note 7)
0.6 µs
0.6 µs
1.3 µs
0.6 µs
100 ns
0 0.9 µs
Maximum Receive SCL/SDA Rise
Time
tR (Note 8)
300 ns
Minimum Receive SCL/SDA Rise
Time
tR (Note 8)
20 + 0.1CB
ns
Maximum Receive SCL/SDA Fall
Time
tF (Note 8)
300 ns
Minimum Receive SCL/SDA Fall
Time
Transmit SDA Fall Time (Note 4)
Pulse Width of Suppressed Spike
tF (Note 8)
tF CB = 400pF, ISDA = 3mA, VL ≥ 2.5V
tF CB = 50pF, ISDA = 3mA, VL < 2.5
tSP (Note 9)
20 + 0.1CB
20 + 0.1CB
20 + 0.1CB
50
250
250
ns
ns
ns
Note 3: All currents into the device are negative; currents out of the device are positive. All voltages are referenced to device
ground unless otherwise specified.
Note 4: Parameters are 100% production tested at +25°C, limits over temperature are guaranteed by design.
Note 5: The VBUS current source and current gate time vary together with process and temperature such that the resulting VBUS
pulse is guaranteed to drive a <13µF load to a voltage >2.0V, and to drive a >96µF load to a volatge <2.2V. See the SRP
VBUS Pulsing section for an explanation of this self-timed pulse.
Note 6: Guaranteed by design, not production tested.
Note 7: A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL’s falling
edge.
Note 8: CB is total capacitance of one bus line in pF. Tested with CB = 400pF.
Note 9: Input filters on SDA, SCL, and ADD suppress noise spikes less than 50ns.
_______________________________________________________________________________________ 5
5 Page 
USB On-the-Go Charge Pump with Switchable
Pullup/Pulldown Resistors
SDA
SCL
S
START
CONDITION
P
STOP
CONDITION
Figure 5. Start and Stop Conditions
bidirectional communication between master(s) and
slave(s). A master (typically a microcontroller) initiates
all data transfers to and from the MAX3353E and gen-
erates the SCL clock that synchronizes the data trans-
fer (Figure 4).
The MAX3353E SDA line operates as both an input and
an open-drain output. A pullup resistor (4.7kΩ typ) is
required on SDA. The MAX3353E SCL line operates
only as an input. A pullup resistor (4.7kΩ typ) is
required on SCL if there are multiple masters on the 2-
wire interface, or if the master in a single-master system
has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 5) sent by a master, followed by the MAX3353E
7-bit slave address plus R/W bit (Figure 6), a register
address byte, one or more data bytes, and finally a
STOP condition (Figure 5).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning the SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 5).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high (Figure 7).
Acknowledge
The acknowledge bit is the clocked ninth bit that the
recipient uses to handshake receipt of each byte of
data (Figure 8). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX3353E, the
MAX3353E generates the acknowledge bit because it
is the recipient. When the MAX3353E is transmitting to
the master, the master generates the acknowledge bit
because the master is the recipient.
Slave Address
The MAX3353E has a 7-bit-long slave address. The
eighth bit following the 7-bit slave address is the R/W
bit. It is low for a write command, high for a read com-
mand. The first 6 bits (MSBs) of the MAX3353E slave
address are always 010110. Select slave address bit
A0 by connecting the address input ADD to VL, GND,
or leave floating (ADD is internally pulled to GND
through a 110kΩ resistor). The MAX3353E has two pos-
sible slave addresses (Table 1). As a result, only two
MAX3353E devices can share the same interface.
Write Byte Format
A write to the MAX3353E comprises the transmission of
the MAX3353E’s slave address with the R/W bit set to
zero, followed by 2 bytes of information. The first byte
of information is the command byte that determines
which register of the MAX3353E is to be written by the
second byte. The second byte is the data that goes into
the register that is set by the first byte. Figure 9 shows
the typical write byte format.
Read Byte Format
A read from the MAX3353E comprises the transmission
of the MAX3353E’s slave address (from the master)
with the R/W bit set to zero, followed by one byte con-
taining the address of the register, from which the mas-
ter is going to read data, and then followed by
MAX3353E’s slave address again with the R/W bit set
to one. After that one byte of data is being read by the
master. Figure 10 shows the read byte format that must
be used. To read many contiguous registers, multiple
accesses are required.
Registers
Control Registers (10h, 11h)
There are two read/write control registers. Control reg-
ister 1 is used to set D+, D- pullup or pulldown, and to
set interrupt output to open-drain or push-pull. Control
register 2 is the bus control register used to control the
bus operation and put the device into shutdown mode.
(Tables 3, 4, and 5.)
Status Register (13h)
The status register is a read-only register for determining
valid bus and session comparator thresholds, ID_IN sta-
tus, and HNP success. Tables 6 and 7 show status regis-
ter address map, bit configuration, and description.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet MAX3353E.PDF ] | |
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