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PDF PI74SSTU32864 Data sheet ( Hoja de datos )
| Número de pieza | PI74SSTU32864 | |
| Descripción | Configurable Registered Buffer | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI74SSTU32864
25-Bit 1:1 or 14-Bit 1:2 Configurable
Registered Buffer
Features
• PI74 SSTU32864 is designed for low-voltage operation,
VDD = 1.8V
• Supports Low Power Standby Operation
• All Inputs are SSTL_18 Compatible, except RST, C0, C1,
which are LVCMOS.
• Output drivers are optimized to drive DDR-II DIMM loads
• Designed for DDR Memory
• Packaging (Pb-free & Green available):
-96 Ball LFBGA (NB)
Block Diagram 1:2 Mode (Positive Logic)
RST
CK
CK
VREF
DCKE
DODT
DCS
1D
C1
R
1D
C1
R
1D
C1
R
QCKEA
QCKEB*
QODTA
QODTB*
QCSA
QCSB*
CSR
D1
0
1 1D
Q1A
C1
R Q1B*
TO OTHER CHANNELS
Note: Disabled in 1:1 configuration
Description
Pericom Semiconductor’s PI74SSTU32864 logic circuit is produced
using advanced CMOS technology. This 25-Bit 1:1 or 14-Bit 1:2
configurable registered buffer is designed for 1.7V to 1.9V VDD
operation.
All clock and data inputs are compatible with the JEDEC standard
for SSTL_18. The control inputs are LVCMOS. All outputs are
1.8V LVCMOS drivers that have been optimized to drive the
DDR-II DIMM load.
The SSTU32864 operates from a differential clock (CK and CK).
Data is registered at the crossing of CK going high, and CK going
low.
The C0 input controls the pinout configuration of the 1:2 pinout
from A configuration (when LOW) to B configuration (when
HIGH). The C1 input controls the pinout configuration for 25-Bit
1:1 (when LOW) to 14-Bit 1:2 (when HIGH).
The device supports low-power standby operation. When the reset
input (RST) is low, the differential input receivers are disabled and
undriven (floating) data, clock and reference voltage (VREF) inputs
are allowed. In addition , when RST is low, all registers are reset,
and all outputs are forced low. The LVCMOS RST and Cn inputs
must always be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has
been supplied, RST must be held in the low state during power up.
In the DDR-II RDIMM application, RSTis specified to be completely
asynchronous with respect to CK and CK. Therefore, no timing
relationship can be guaranteed between the two. When entering
reset, the register will be cleared and the outputs will be driven
low quickly, relative to the time to disable the differential input
receivers. However, when coming out of reset, the register will
become active quickly, relative to the time to enable the differential
input receivers.
As long as the data inputs are low, and the clock is stable during
the time from the low-to-high transition of RST until the input
receivers are fully enabled, the design of the SSTU32864 must
ensure that the outputs remain low, thus ensuring no glitches on
the output.
The device monitors both DCS and CSR inputs and will gate the
Qn outputs from changing states when both DCS and CSR inputs
are high. If either DCS or CSR input is low, the Qn outputs will
function normally.The RSTinput has priority over the DCS and CSR
control will force the outputs low. If the DCS control functionality
is not desired, then the CSR input can be hardwired to ground,
in which case, the set-up time requirement for DCS would be the
same as for the other D data inputs.
1
PS8636B
07/26/04
1 page  
PI74SSTU32864
25-Bit 1:1 or 14-Bit 1:2
Configurable Buffer
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................................... –65°C to +150°C
Supply Voltage Range, VDD .............................................–0.5V to 2.5V
Input Voltage Range,VI : (See Notes 2 and 3): ................–0.5V to 2.5V
Output Voltage Range, VO (See Notes 2 and 3).... –0.5V to VDD + 0.5V
Input Clamp current, IIK (VI < 0 or VI = VDD ) ......................... –50mA
Output Clamp current, IOK (VO < 0 or VO > VDD).................... ±50mA
Continous Output Current, IO (VO = 0 to VDD) ........................ ±50mA
Continous Current through each VDD or GND......................... ±100mA
Notes:
1. Stresses greater than those listed under MAXIMUM
RAINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be ex-
ceeded if the input and output clamp-current ratings are
observed.
3. This value is limited to 2.5V maximum
Recommended Operating Conditions(1)
Parameters
Descrition
VDD Supply Voltage
VREF
Reference Voltage
VTT Termination Voltage
VI Input Voltage
VIH AC High - Level Input Voltage
VIL AC Low- Level Input Voltage
VIH DC High - Level Input Voltage
VIL DC Low- Level Input Voltage
VIH High Level Input Voltage
VIL Low Level Input Voltage
VICR
Common-mode input Voltage
VID Differential Input Voltage
IOH High-Level Output Current
IOL Low-Level Output Current
TA Operating Free-air Temperature
Data
Inputs
Min.
1.7
0.49 x VDD
VREF -40mA
0
VREF 250mV
VREF 125mV
RST, CN
CK, CK
0.65 x VDD
0.675
600
0
Nom.
0.50 x VDD
VREF
Max.
1.9
0.51 x VDD
VREF -40mA
VDD
Units
VREF -250mV
V
VREF -125mV
0.35 x VDD
1.125
-8
-8
70
mV
mA
ºC
Notes:
1. The RST and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must
not be floating, unless RST is low.
5
PS8636B
07/26/04
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet PI74SSTU32864.PDF ] | |
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