PDF SPEAR-09-H122 Data sheet ( Hoja de datos )

Número de pieza	SPEAR-09-H122
Descripción	SPEAr TM Head600
Fabricantes	ST Microelectronics
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No Preview Available ! www.DataSheet4U.com SPEAR-09-H122 SPEAr™ Head600 Preliminary Data Features ■ ARM926EJ-S core @333MHz. ■ 600KByte reconfigurable logic array with 88 dedicated General purposes I/Os, 9 LVDS channels and 128KByte configurable internal memory pool. ■ Multilayer AMBA 2.0 compliant Bus with fMAX 166MHz ■ 32KByte Rom. ■ 8KByte common Static Ram. ■ Dynamic Power saving features. ■ High performance 8 channels DMA. ■ Ethernet 10/100/1000 MAC with GMII/MII Interface to external PHY. ■ USB2.0 device with integrated PHY. ■ 2 USB2.0 Host with integrated PHY. ■ Ext. SDRAM memory interface: – 8/16bit (DDR1@200MHz) – 8/16bit (DDR2@333MHz) ■ Flashes interface: – Nand 8/16bit – Serial (up to 50Mbps). ■ 3-SPI Master/Slave up to 40Mbps. ■ I2C Master/Slave mode - High, Fast and Slow speed. ■ 2 independent UART up to 460.8 Kbps with Software Flow Control mode. ■ IrDA (Fir-Mir-Sir) from 9.6Kbps to 4Mbps speed-rate. ■ Colour LCD controller: – up to 1024x768 resolutions. PBGA420 – 24bpp true colour TFT panel. – 16bpp DSTN panel. ■ 10 GPIOs bidirectional signals with interrupt capability. ■ 88 RAS-GPIOs user customizable bidirectional signals (up to 4 clocks). ■ ADC 10 bit, 1MSPS, 8 analog inputs. ■ JPEG codec accelerator. ■ 10 independent Timers with programmable prescaler. ■ Real Time Clock. ■ WatchDog ■ System Controller ■ MISC internal control registers. ■ JTAG (IEEE1149.1) interface Description SPEAr Head600 is a powerful digital engine belonging to SPEAr family, the innovative customizable System on chip. The device integrates an ARM 926 core with a large set of proven IPs and a big configurable logic block that allow very fast customization of unique and/or proprietary solution. Table 1. Device summary Part number Op. temp. range, °C SPEAR-09-H122 -40 to 85 Package PBGA420(23x23x1.81mm) Packing Tray February 2007 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/37 www.st.com 1 1 page SPEAR-09-H122 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Main SPEAr Head600 functional interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 RTC crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 RTC crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PBGA420 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5/37 5 Page SPEAR-09-H122 Pin description Table 2. Group PL Pin description by functional group (continued) Signal name Ball Direction Function Pin Type PL_GPIO_1 N4 PL_GPIO_2 N5 PL_GPIO_3 PL_GPIO_4 N6 M5 PL_GPIO_5 M4 PL_GPIO_6 M3 PL_GPIO_7 M2 PL_GPIO_8 PL_GPIO_9 M1 L1 PL_GPIO_10 L2 PL_GPIO_11 L3 PL_GPIO_12 L4 PL_GPIO_13 PL_GPIO_14 L5 K6 PL_GPIO_15 K5 PL_GPIO_16 K4 PL_GPIO_17 PL_GPIO_18 PL_GPIO_19 K3 TTL BIDIR buffer, K2 I/O Programmable Logic I/O 3.3V capable, 4mA K1 3.3V tolerant, PU PL_GPIO_20 J1 PL_GPIO_21 J2 PL_GPIO_22 PL_GPIO_23 J3 J4 PL_GPIO_24 J5 PL_GPIO_25 H5 PL_GPIO_26 PL_GPIO_27 H4 H3 PL_GPIO_28 H2 PL_GPIO_29 H1 PL_GPIO_30 G1 PL_GPIO_31 PL_GPIO_32 G2 G3 PL_GPIO_33 G4 PL_GPIO_34 G5 PL_GPIO_35 F5 11/37 11 Page

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Número de pieza	Descripción	Fabricantes
SPEAR-09-H122	SPEAr TM Head600	ST Microelectronics

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