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PDF SPEAR-09-H022 Data sheet ( Hoja de datos )
| Número de pieza | SPEAR-09-H022 | |
| Descripción | large IP portfolio SoC | |
| Fabricantes | ST Microelectronics | |
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SPEAR-09-H022
SPEAr™ Head
ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC
PRELIMINARY DATA
Features
■ ARM926EJ-S - fMAX 266 MHz,
32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and
JTAG interfaces
■ 200K customizable equivalent ASIC gates
(16K LUT equivalent) with 8 channels internal
DMA high speed accelerator function and 112
dedicated general purpose I/Os
■ Multilayer AMBA 2.0 compliant Bus with
fMAX 133 MHz
■ Programmable internal clock generator with
enhanced PLL function, specially optimized for
E.M.I. reduction
■ 16 KB single port SRAM embedded
■ Dynamic RAM interface:
16 bit DDR, 32 / 16 bit SDRAM
■ SPI interface connecting serial ROM and Flash
devices
■ 2 USB 2.0 Host independent ports with
integrated PHYs
■ USB 2.0 Device with integrated PHY
■ Ethernet MAC 10/100 with MII management
interface
■ 3 independent UARTs up to 115 Kbps
(Software Flow Control mode)
■ I2C Master mode - Fast and Slow speed
■ 6 General Purpose I/Os
PBGA420
■ ADC 8 bits, 230 Ksps, 16 analog input
channels
■ Real Time Clock
■ WatchDog
■ 4 General Purpose Timers
■ Operating temperature: - 40 to 85 °C
■ Package: PBGA 384+36 6R (23x23x2.16 mm)
Overview
SPEAr Head is a powerful digital engine
belonging to SPEAr family, the innovative
customizable System on Chips.
The device integrates an ARM core with a large
set of proven IPs (Intellectual Properties) and a
configurable logic block that allows very fast
customization of unique and/or proprietary
solutions, with low effort and low investment.
Optimized for embedded applications.
Order codes
Part number
SPEAR-09-H022
Op. Temp. range, °C
-40 to 85
Package
PBGA420 (23x23x2.16 mm)
Packing
Tray
December 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Rev 2
1/55
www.st.com
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1 page  
SPEAR-09-H022
1 Reference Documentation
[1] ARM926EJ-S - Technical Reference Manual
[2] AMBA 2.0 Specification
[3] EIA/JESD8-9 Specification
[4] USB2.0 Specification
[5] OCHI Specification
[6] ECHI Specification
[7] UTMI Specification
[8] USB Specification
[9] IEEE 802.3 Specification
[10] I2C - Bus Specification
1 Reference Documentation
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5 Page 
SPEAR-09-H022
● RX FIFO (512x36 Dual Port)
● AHB DMA master connected to memory system
● AHB slave for configuration
3 Features
3.7 LOW SPEED CONNECTIVITY
UART
● Support for 8 bit serial data TX and RX
● Selectable 2 / 1 Stop bits
● Selectable Even, Odd and No Parity
● Parity, Overrun and Framing Error detector
● Max transfer rate: 115 Kbps
I2C
● Standard I2C mode (100 KHz) / Fast I2C mode (400 KHz)
● Master interface only
● Master functions control all I2C bus specific sequencing, protocol, arbitration and timing
● Detection of bus errors during transfers
3.8 GENERAL POURPOSE I/Os
6 programmable GP I/Os
3.9 ANALOG TO DIGITAL CONVERTER
● 8 bit resolutions
● 230 Ksps
● 16 analog input channels (0 - 3.3 V)
● INL ± 1 LSB
● DNL ± 0.5 LSB
● Programmable conversion speed - minimum conversion time 4.3 µs
3.10 REAL TIME CLOCK
● Real time clock-calendar (RTC)
● 14 digit (YYYY MM DD hh mm ss) precision
● Clocked by 32.768 KHz low power clock input
● Separated power supply (1.2 V)
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