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PDF AK4633 Data sheet ( Hoja de datos )
| Número de pieza | AK4633 | |
| Descripción | 16-Bit Mono CODEC | |
| Fabricantes | AKM | |
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ASAHI KASEI
www.DataSheet4U.com
[AK4633]
AK4633
16-Bit ∆Σ Mono CODEC with ALC & MIC/SPK-AMP
GENERAL DESCRIPTION
The AK4633 is a 16-bit mono CODEC with Microphone-Amplifier and Speaker-Amplifier. Input circuits
include a Microphone-Amplifier and an ALC (Automatic Level Control) circuit. Output circuits include a
Speaker-Amplifier and Mono Line Output. The AK4633 suits a moving picture of Digital Still Camera and
etc. This speaker-Amplifier supports a Piezo Speaker. The AK4633 is housed in a space-saving 24-pin
QFN package.
FEATURE
1. 16-Bit Delta-Sigma Mono CODEC
2. Recording Function
• 1ch Mono Input
• 1st MIC Amplifier: 0dB, 6dB, 10dB, 14dB, 17dB, 20dB, 26dB or 32dB
• 2nd Amplifier with ALC: +36dB ∼ -54dB, 0.375dB Step, Mute
• ADC Performance (MIC-Amp= +20dB): S/(N+D): 84dB, DR, S/N: 85dB
• Wind Noise Reduction
• Notch Filter
3. Playback Function
• Digital ALC (Automatic Level Control): +36dB ∼ -54dB, 0.375dB Step, Mute
• Mono Line Output Performance: S/(N+D): 85dB, S/N: 93dB
• Mono Speaker-Amp
- Speaker-Amp Performance: S/(N+D): 60dB (150mW@ 8Ω)
Output Noise Level: -87dBV
- BTL Output
- Output Power: 400mW @ 8Ω
• Beep Input
4. Power Management
5. Flexible PLL Mode:
• Frequencies:
11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin)
1fs (FCK pin)
16fs, 32fs or 64fs (BICK pin)
6. EXT Mode:
• Frequencies: 256fs, 512fs or 1024fs (MCKI pin)
7. Sampling Rate:
• PLL Slave Mode (FCK pin) : 7.35kHz ~ 48kHz
• PLL Slave Mode (BICK pin) : 7.35kHz ~ 48kHz
• PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• EXT Slave Mode/EXT Master Mode:
7.35kHz~ 48kHz (256fs), 7.35kHz ~ 26kHz (512fs), 7.35kHz ~ 13kHz (1024fs)
8. Output Master Clock Frequency: 256fs
9. Serial µP Interface: 3-wire
10. Master / Slave Mode
MS0447-E-03
-1-
2006/04
1 page  
ASAHI KASEI
[AK4633]
2. Register Map
(1) AK4631
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Input PGA Control
Digital Volume Control
ALC2 Mode Control
D7
0
0
SPPS
0
PLL3
0
DVTM
0
0
0
OVOL7
0
D6
PMVCM
0
BEEPS
AOPSN
PLL2
0
ROTM
ALC2
REF6
IPGA6
OVOL6
0
D5
PMBP
0
ALC2S
MGAIN1
PLL1
FS3
ZTM1
ALC1
REF5
IPGA5
OVOL5
RFS5
D4
PMSPK
0
DACA
SPKG1
PLL0
MSBS
ZTM0
ZELM
REF4
IPGA4
OVOL4
RFS4
D3
PMAO
M/S
DACM
SPKG0
BCKO1
BCKP
WTM1
LMAT1
REF3
IPGA3
OVOL3
RFS3
D2
PMDAC
MCKPD
MPWR
BEEPA
BCKO0
FS2
WTM0
LMAT0
REF2
IPGA2
OVOL2
RFS2
D1
PMMIC
MCKO
MICAD
ALC1M
DIF1
FS1
LTM1
RATT
REF1
IPGA1
OVOL1
RFS1
D0
PMADC
PMPLL
MGAIN0
ALC1A
DIF0
FS0
LTM0
LMTH
REF0
IPGA0
OVOL0
RFS0
(2) AK4633
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0DH
0EH
Register Name
Power Management 1
Power Management 2
Signal Select 1
Signal Select 2
Mode Control 1
Mode Control 2
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Digital Volume Control
Digital Volume Control
ALC Mode Control 3
ALC LEVEL
Signal Select 3
10H - 1FH
D7
PMPFIL
0
SPPSN
PFSDO
PLL3
ADRST
0
0
IREF7
IVOL7
OVOL7
RGAIN1
VOL7
DATT1
hatching
Bold
D6 D5 D4 D3
PMVCM PMBP PMSPK PMAO
0 0 0 M/S
BEEPS DACS DACA
0
AOPS MGAIN1 SPKG1 SPKG0
PLL2
PLL1
PLL0 BCKO1
FCKO
FS3
MSBS
BCKP
0
ZTM1
ZTM0
WTM1
ALC2
ALC1 ZELMN LMAT1
IREF6
IREF5
IREF4
IREF3
IVOL6 IVOL5 IVOL4 IVOL3
OVOL6 OVOL5 OVOL4 OVOL3
LMTH1 OREF5 OREF4 OREF3
VOL6 VOL5 VOL4 VOL3
DATT0 SMUTE MDIF
EQ2
Digital Filter Setting
Register bits changed from the AK4631.
Register bits added from the AK4631.
D2
PMDAC
0
PMMP
BEEPA
BCKO0
FS2
WTM0
LMAT0
IREF2
IVOL2
OVOL2
OREF2
VOL2
EQ1
D1
0
MCKO
MGAIN2
PFDAC
DIF1
FS1
RFST1
RGAIN0
IREF1
IVOL1
OVOL1
OREF1
VOL1
HPF
D0
PMADC
PMPLL
MGAIN0
ADCPF
DIF0
FS0
RFST0
LMTH0
IREF0
IVOL0
OVOL0
OREF0
VOL0
HPFAD
MS0447-E-03
-5-
2006/04
5 Page 
ASAHI KASEI
[AK4633]
Parameter
Min typ max Units
Speaker-Amp Characteristics: DAC Æ SPP/SPN pins, ALC2=OFF, CL=3µF, Rserial=10Ω x 2, BTL, SVDD=3.8V
Output Voltage
SPKG1-0 bits = “11”
(-4.1dBFS)
-
6.33
- Vpp
S/(N+D) (Note 13)
SPKG1-0 bits = “11”
(-4.1dBFS)
-
60
- dB
Output Noise Level (Note 13) SPKG1-0 bits = “11”
-
-81
- dBV
Load Impedance (Note 14)
50 -
-Ω
Load Capacitance
- - 3 µF
BEEP Input: BEEP pin, External Input Resistance= 20kΩ
Maximum Input Voltage (Note 15)
- 1.98 - Vpp
Output Voltage (Input Voltage=0.6Vpp)
BEEP Æ SPP/SPN (SPKG1-0 bits = “00”)
0.625
1.25
1.875
Vpp
BEEP Æ AOUT
0.25 0.50 0.75 Vpp
Power Supplies
Power Up (PDN = “H”)
All Circuit Power-up: (Note 17)
AVDD+DVDD
fs=8kHz
-8
fs=48kHz
- 11
SVDD: Speaker-Amp Normal Operation (SPPSN bit = “1”, No Output)
SVDD=3.3V
-4
Power Down (PDN = “L”) (Note 18)
AVDD+DVDD+SVDD
-1
- mA
17 mA
12 mA
100 µA
Note 8. It is a differential value of plus and minus input pin. Each input pins should be connected to the AC coupling
capacitance serially. The differential input is not permission when MGAIN2-0 bits are “000”. The Maximum
input voltage of MICP and MICN pins are proportional to AVDD voltage. Vin= |(MICP) − (MICN)| = 0.069 x
AVDD (max)@MGAIN2-0 bits = “001”,
0.035 x AVDD (max)@MGAIN2-0 bits = “010”, 0.017 x AVDD (max)@MGAIN2-0 bits = “011”,
0.346 x AVDD (max)@MGAIN2-0 bits = “100”, 0.218 x AVDD (max)@MGAIN2-0 bits = “101”,
0.138 x AVDD (max)@MGAIN2-0 bits = “110”, 0.098 x AVDD (max)@MGAIN2-0 bits = “111”,
ADC function is not assumed for using the exceeded input voltage.
Note 9. Output Voltage is proportional to AVDD voltage. Vout = 0.8 x AVDD (typ).
Note 10. Input Voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ).
Note 11. When a PLL reference clock is FCK pin in PLL Slave Mode, S/(N+D):MICÆADC is 75dB (typ) and
S/(N+D):DACÆAOUT is 75dB(typ).
Note 12. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).
Note 13. In case of measuring between SPP pin and SPN pin directly.
Note 14. Load impedance is total impedance of series resistance and piezo speaker impedance at 1kHz in Figure 41. Load
capacitance is capacitance of piezo speaker. When piezo speaker is used, 10Ω or more series resistors should be
connected at both SPP and SPN pins, respectively.
Note 15. The maximum input voltage of the BEEP is proportional to AVDD voltage and external input resistance (Rin).
Vout = 0.6 x AVDD x Rin/20kΩ(max).
Note 16. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).
Note 17. In case of PLL Master Mode (MCKI=12.288MHz) and PMMP = PMADC = PMDAC = PMPFIL = PMSPK =
PMVCM = PMPLL = MCKO = PMAO = PMBP = PMMP = M/S =“1”. In this case, the output current of MPI
pin is 0mA.
When the AK4633 is EXT mode (PMPLL = MCKO = M/S = “0”), “AVDD+DVDD” is typically 6mA@fs=8kHz,
9mA@fs=48kHz.
Note 18. All digital inputs pins are fixed to DVDD or DVSS.
MS0447-E-03
- 11 -
2006/04
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK4633.PDF ] | |
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