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PDF ISL90842 Data sheet ( Hoja de datos )
| Número de pieza | ISL90842 | |
| Descripción | Low Noise/Low Power/I2C Bus/256 Taps | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
ISL90842
Quad Digital Controlled Potentiometers (XDCP™)
June 14, 2005
FN8096.0
Low Noise, Low Power, I2C® Bus,
256 Taps
The ISL90842 integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
Wiper Register (WR) that can be directly written to and read
by the user. The contents of the WR controls the position of
the wiper.
The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Ordering Information
PART NUMBER
ISL90842UIV1427
ISL90842WIV1427
PACKAGE
14 Ld TSSOP
14 Ld TSSOP
RESISTANCE
OPTION
50kΩ
10kΩ
Features
• Four potentiometers in one package
• 256 resistor taps–0.4% resolution
• I2C serial interface
• Wiper resistance: 70Ω typical @ 3.3V
• Standby current <5µA max
• Power supply: 2.7V to 5.5V
• 50kΩ, 10kΩ total resistance
• 14 Lead TSSOP
Pinout
ISL90842
(14 LEAD TSSOP)
TOP VIEW
RH3
RW3
SCL
SDA
GND
RW2
RH2
1
2
3
4
5
6
7
14 RW0
13 RH0
12 VCC
11 A1
10 A0
9 RH1
8 RW1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL90842
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (NOTE 1)
tHD:STO STOP condition hold time for From SDA rising edge to SCL falling edge. Both crossing
read, or volatile only write
70% of VCC.
tDH Output data hold time
(Note 15)
From SCL falling edge crossing 30% of VCC, until SDA
enters the 30% to 70% of VCC window.
tR SDA and SCL rise time
(Note 15)
From 30% to 70% of VCC
600
0
20 +
0.1 * Cb
tF SDA and SCL fall time
(Note 15)
From 70% to 30% of VCC
20 +
0.1 * Cb
Cb Capacitive loading of SDA or Total on-chip and off-chip
(Note 15) SCL
10
Rpu SDA and SCL bus pull-up
(Note 15) resistor off-chip
Maximum is determined by tR and tF.
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ
1
tSU:A
tHD:A
A1 and A0 setup time
A1 and A0 hold time
Before START condition
After STOP condition
600
600
MAX
250
250
400
UNITS
ns
ns
ns
ns
pF
kΩ
ns
ns
SDA vs SCL Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tSU:DAT
tHD:STA
tHD:DAT
tAA tDH
tSU:STO
tBUF
A0 and A1 Pin Timing
SCL
START
SDA IN
A0, A1
tSU:A
CLK 1
STOP
tHD:A
5 FN8096.0
June 14, 2005
5 Page 
ISL90842
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL90842 responds with an ACK. At this time, the device
enters its standby state (See Figure 17).
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL90842 responds with an ACK. Then the ISL90842
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a
STOP condition) following the last bit of the last Data Byte
(See Figure 18).
The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 03h the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
11 FN8096.0
June 14, 2005
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ISL90842.PDF ] | |
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