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PDF AX88170L Data sheet ( Hoja de datos )
| Número de pieza | AX88170L | |
| Descripción | USB to Fast Ethernet/HomePNA Controller | |
| Fabricantes | ASIX Electronics | |
| Logotipo |  |
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AX88170 L
USB to Fast Ethernet/HomePNA Controller
USB to Fast Ethernet/HomePNA Controller
Document No.: AX170-12 / V1.2 / Apr. 11 ’01
Features
• Single chip USB to 10/100Mbps Fast Ethernet and
• Provides optional MII/RMII interface with PHY
1/10Mbps HomePNA Network Controller
• Compliant with USB specification 1.0 and 1.1
mode for multiple ports USB-to-USB bridge
application.
• Full Speed USB Device with bus power capability
• USB Communication Class Spec 1.0 Compliant
• Support 4 endpoints on USB
• IEEE 802.3u 100BASE-T, TX, and T4 Compatible
• Embedded 5K*16 bit SRAM
• Support both full-duplex or half-duplex operation on
Fast Ethernet
• Provides a MII port for both Ethernet and
• Support 256/512 bytes serial EEPROM (used for
saving USB Descriptors)
• Support automatic loading of Ethernet ID, USB
Descriptors and Adapter Configuration from
EEPROM on power-on initialization
• External PHY loop-back diagnostic capability
• Small form factor 64-pin LQFP package
• 48MHz and 25MHz Operation, pure 3.3V operation
HomePNA PHY interface
• Supports suspended mode and remote wakeup
(link_up or magic packet)
• Optional PHY power down mode for power saving
with I/O 5V tolerance
*IEEE is a registered trademark of the Institute of Electrical and
Electronic Engineers, Inc.
*All other trademarks and registered trademark are the property of
their respect ive holders.
Product description
The AX88170 USB to Fast Ethernet/HomePNA Controller is a high performance and highly integrated Controller with
embedded 5K*16 bit SRAM. The AX88170 contains a USB interface to host CPU and compliant with USB StandardV1.0 and
V1.1. The interface between AX88170 and PC Host is compliant with USB Communication Class Specification 1.0. The
AX88170 could be used for both 10M/100Mbps Fast Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard and
1M/10M HomePNA standard. The AX88170 supports media-independent interface (MII) or RMII (Reduce MII) interface to
simplify the design on implementing Fast Ethernet and HomePNA functions. The chip also provides an optional MII/RMII
interface with PHY mode, combine with Ethernet repeater or switch IC can build a multiple ports USB-to-USB bridge
application.
System Block Diagram
RJ45
MAGNETIC
10/100 Mbps Ethernet
PHY/TxRx
RJ11
MAGNETIC
1/10 Mbps
Home LAN PHY
AX88170
EEPROM
USB I/F
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
Frist Released Date : Sep/11/2000
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
1 page  
AX88170
CONFIDENTIAL
PRELIMINARY
1.3 AX88170 Pin Connection Diagram with MII Interface
The AX88170 is housed in the 64-pin plastic light quad flat pack. See Fig – 2 AX88170 Pin Connection
Diagram.
VSS
VDD
48M_XOUT
48M_XIN
VSS
VDD
TEST0
TEST1
TEST2
TEST3
VDD
TEST_OUT
TEST4
LD_RDY
ACT/LINK
VSS
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
ASIX
AX88170
(MII Interface)
32 RX_DV
31 RX_ER
30 VDD
29 RXD3
28 RXD2
27 RXD1
26 RXD0
25 VSS
24 RX_CLK
23 VDD
22 TX_EN
21 TXD3
20 TXD2
19 TXD1
18 TXD0
17 VSS
Fig – 2 AX88170 Pin Connection Diagram with MII Interface
5
ASIX ELECTRONICS CORPORATION
5 Page 
AX88170
CONFIDENTIAL
PRELIMINARY
3.0 EEPROM Memory Mapping
EEPROM
OFFSET
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H-18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H-4FH
50H-FFH
HIGH BYTE
LOW BYTE
RESERVED
WORD COUNT FOR PRELOAD
*FLAG
LENGTH OF DEVICE DESCRIPTOR (BYTE)
EEPROM OFFSET OF DEVICE
DESCRIPTOR
LENGTH OF CONFIGURATION DESCRIPTOR
EEPROM OFFSET OF CONFIGURATION
(BYTE)
DESCRIPTOR
NODE ID 1
NODE ID 0
NODE ID 3
NODE ID 2
NODE ID 5
NODE ID 4
LANGUAGE ID HIGH BYTE
LANGUAGE ID LOW BYTE
LENGTH OF STRING INDEX 1
EEPROM OFFSET OF STRING INDEX 1
LENGTH OF STRING INDEX 2
EEPROM OFFSET OF STRING INDEX 2
LENGTH OF STRING INDEX 3
EEPROM OFFSET OF STRING INDEX 3
LENGTH OF STRING INDEX 4
EEPROM OFFSET OF STRING INDEX 4
LENGTH OF STRING INDEX 5
EEPROM OFFSET OF STRING INDEX 5
LENGTH OF STRING INDEX 6
EEPROM OFFSET OF STRING INDEX 6
LENGTH OF STRING INDEX 7
EEPROM OFFSET OF STRING INDEX 7
LENGTH OF STRING INDEX 8
EEPROM OFFSET OF STRING INDEX 8 (19H)
MAX PACKETSIZE HIGH BYTE
MAX PACKET LOW BYTE
HOMEPNA PHY ID
ETHERNET PHY ID
PAUSE PACKET HIGH WATER LEVEL
PAUSE PACKET LOW WATER LEVEL
RESERVED
03H 0CH
BYTE 2 OF UNICODE MAC ADDRESS
**BYTE 1 OF UNICODE MAC ADDRESS
BYTE 4 OF UNICODE MAC ADDRESS
BYTE 3 OF UNICODE MAC ADDRESS
BYTE 6 OF UNICODE MAC ADDRESS
BYTE 5 OF UNICODE MAC ADDRESS
BYTE 8 OF UNICODE MAC ADDRESS
BYTE 7 OF UNICODE MAC ADDRESS
BYTE 10 OF UNICODE MAC ADDRESS
BYTE 9 OF UNICODE MAC ADDRESS
BYTE 12 OF UNICODE MAC ADDRESS
BYTE 11 OF UNICODE MAC ADDRESS
DEVICE /CONFIGURATION /INTERFACE /ENDPOINT DESCRIPTOR
STRINGS
Tab - 7 EEPROM Memory Mapping
Note:
*Flag:
Bit 0 è Self Powered (for USB GetStatus) Bit 1 è Bus Powered (Reserved)
Bit 2 è Remote Wakeup (for USB GetStatus) Bit 3 è Interrupt Endpoint Enaable (Reserved)
Bit 4 è ClkNoStop (for Self Power only)
Bit 5 è Reserved
Bit 6 è Reserved
Bit 7 è Reserved
Bit 8 è Capture Effective Mode
Bit 9è Flow Control selector (1: software,o: read from PHY)
Bit A – F è Reserved
Bit 4 also effect LED display, if high then LED display USB active only otherwise display USB link and activity.
(In Self power mode Bit_4 set to high)
**Unicode MAC Address:
If the MAC’s NODE ID is 01,23,45,67,89,ABh respect to NODE ID 0, NODE ID 1, … NODE ID5
Then
the unicode will be 30-31,32-33,34-35,36-37,38-39,41-42h respects to BYTE 1 OF UNICODE MAC ADDRESS- BYTE
2 OF UNICODE MAC ADDRESS, … -BYTE 12 OF UNICODE MAC ADDRESS.
11 ASIX ELECTRONICS CORPORATION
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