|
|
Número de pieza | 74AUP1G3208 | |
Descripción | Low Power 3-Input OR-AND Gate | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de 74AUP1G3208 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
No Preview Available ! www.DataSheet4U.com
74AUP1G3208
Low-power 3-input OR-AND gate
Rev. 01 — 29 November 2006
Product data sheet
1. General description
The 74AUP1G3208 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G3208 provides the Boolean function: Y = (A + B) × C. The user can choose
the logic functions OR, AND and OR-AND. All inputs can be connected to VCC or GND.
2. Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-12 (0.8 V to 1.3 V)
x JESD8-11 (0.9 V to 1.65 V)
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114-D Class 3A exceeds 5000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Low static power consumption; ICC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from −40 °C to +85 °C and −40 °C to +125 °C
1 page www.DataSheet4U.com
NXP Semiconductors
74AUP1G3208
Low-power 3-input OR-AND gate
9. Recommended operating conditions
Table 7.
Symbol
VCC
VI
VO
Tamb
∆t/∆V
Recommended operating conditions
Parameter
Conditions
supply voltage
input voltage
output voltage
Active mode
ambient temperature
Power-down mode; VCC = 0 V
input transition rise and fall rate VCC = 0.8 V to 3.6 V
10. Static characteristics
Min Max Unit
0.8 3.6 V
0 3.6 V
0
VCC
V
0 3.6 V
−40 +125 °C
0 200 ns/V
Table 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Typ
Tamb = 25 °C
VIH HIGH-level input voltage
VCC = 0.8 V
VCC = 0.9 V to 1.95 V
0.70 × VCC -
0.65 × VCC -
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
1.6 -
2.0 -
VIL LOW-level input voltage VCC = 0.8 V
VCC = 0.9 V to 1.95 V
--
--
VCC = 2.3 V to 2.7 V
--
VCC = 3.0 V to 3.6 V
--
VOH HIGH-level output voltage VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VCC − 0.1 -
0.75 × VCC -
1.11 -
1.32 -
2.05 -
1.9 -
2.72 -
2.6 -
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
-
-
IO = 1.1 mA; VCC = 1.1 V
--
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
--
--
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
--
--
IO = 2.7 mA; VCC = 3.0 V
--
IO = 4.0 mA; VCC = 3.0 V
--
Max Unit
-V
-V
-V
-V
0.30 × VCC V
0.35 × VCC V
0.7 V
0.9 V
-V
-V
-V
-V
-V
-V
-V
-V
0.1
0.3 × VCC
0.31
0.31
0.31
0.44
0.31
0.44
V
V
V
V
V
V
V
V
74AUP1G3208_1
Product data sheet
Rev. 01 — 29 November 2006
© NXP B.V. 2006. All rights reserved.
5 of 16
5 Page www.DataSheet4U.com
NXP Semiconductors
13. Package outline
Plastic surface-mounted package; 6 leads
DB
74AUP1G3208
Low-power 3-input OR-AND gate
SOT363
E AX
y
6
54
pin 1
index
12
e1 bp
e
3
wM B
HE v M A
A
A1
Q
Lp
detail X
c
01
scale
2 mm
DIMENSIONS (mm are the original dimensions)
UNIT A
A1
max
bp
c
D
E
e
e1 HE Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.30 0.25
0.20 0.10
2.2
1.8
1.35 1.3
1.15
0.65
2.2 0.45 0.25
2.0 0.15 0.15
0.2
0.2
0.1
OUTLINE
VERSION
SOT363
IEC
REFERENCES
JEDEC
JEITA
SC-88
Fig 11. Package outline SOT363 (SC-88)
74AUP1G3208_1
Product data sheet
Rev. 01 — 29 November 2006
EUROPEAN
PROJECTION
ISSUE DATE
04-11-08
06-03-16
© NXP B.V. 2006. All rights reserved.
11 of 16
11 Page |
Páginas | Total 16 Páginas | |
PDF Descargar | [ Datasheet 74AUP1G3208.PDF ] |
Número de pieza | Descripción | Fabricantes |
74AUP1G3208 | Low Power 3-Input OR-AND Gate | NXP Semiconductors |
Número de pieza | Descripción | Fabricantes |
SLA6805M | High Voltage 3 phase Motor Driver IC. |
Sanken |
SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |