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PDF MTD516 Data sheet ( Hoja de datos )

Número de pieza MTD516
Descripción 16 Port 10M/100M Ethernet Switch
Fabricantes Myson 
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MYSON
MTD516
TECHNOLOGY
(Preliminary)
16 Port 10M/100M Ethernet Switch
FEATURES
GENERAL DESCRIPTION
• IEEE802.3 and IEEE802.3u compliant.
• Provide 16 RMII (Reduced Media Independent
Interface) ports.
• Programmable 1K/8K MAC addresses filtering
database.
• Store and forward switching function and bad
packet filtering function.
• Optional back_pressure/802.3x flow control/
flooding control/broadcast control.
• Optional EEPROM Interface for advanced
switch configurations.
• 4MB/2MB packet buffer with SGRAM/SDRAM
flexible memory interface.
• Port VLAN/trunking.
• Link/Rx activity, packet buffer utilization LED
display.
• 83MHz for non-blocking 16 port switch.
• Build in internal/external memory test function.
• 208 pin PQFP package, 3.3V operation volt-
age.
The MTD516 complies fully with the
IEEE802.3, 802.3u and 802.3x specifications and
is a non-blocking 16 port 10M/100M Ethernet
switch device.
Support 16 RMII ports for 10M/100M oper-
ation. 4MB memory interface provides maximum
2730 packet buffers for Ethernet packet buffering.
Up to 8192 address entrys are provided by the
MTD516, and the MTD516 use full Ethernet
address compare algorithm to minimize hashing
collision events.
The MTD516 provides EEPROM interface
to config port trunking, port VLAN, static entry,
802.3x flow control threshold, flooding port,
broadcast control threshold. Each MTD516 ports
support 10M/100M auto-negotiation by MII man-
agement interface.
The MTD516 also provides 2 pins for Link/
RX activity, packet buffer utilization LED display
function.
BLOCK DIAGRAM
SDRAM/
SGRAM
Interface
Memory
Controller
DMA0
MAC0
RMII0
Memory
Arbiter
DMA1
DMA2
DMA3
DMA4
MAC1
MAC2
MAC3
MAC4
RMII1
RMII2
RMII3
3~12
RMII12
Port
Switch
Logic
DMA13
DMA14
DMA15
MAC13
MAC14
MAC15
RMII13
RMII14
RMII15
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification
without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of
the product.
1/27 MTD516 Revision 1.2 19/06/2000

1 page




MTD516 pdf
MYSON
TECHNOLOGY
MTD516
(Preliminary)
Name
CRSDV6
RXD6_0
RXD6_1
TXEN6
TXD6_0
TXD6_1
CRSDV7
RXD7_0
RXD7_1
TXEN7
TXD7_0
TXD7_1
CRSDV8
RXD8_0
RXD8_1
TXEN8
TXD8_0
TXD8_1
CRSDV9
RXD9_0
RXD9_1
TXEN9
TXD9_0
TXD9_1
CRSDV10
RXD10_0
RXD10_1
TXEN10
TXD10_0
TXD10_1
CRSDV11
RXD11_0
RXD11_1
TXEN11
TXD11_0
TXD11_1
RMII Port Interface Pins
Pin Number
18
19
20
17
16
15
24
25
26
23
22
21
32
33
34
31
30
29
38
39
40
37
36
35
46
47
48
45
44
43
52
53
54
51
50
49
I/O Descriptions
I Port6 RMII receive interface signal, CRSDV6 is asserted high when
port6 media is non_idle.
I Port6 RMII receive data bit_0.
I Port6 RMII receive data bit_1.
O Port6 RMII transmit enable signal.
O Port6 RMII transmit data bit_0.
O Port6 RMII transmit data bit_1.
I Port7 RMII receive interface signal, CRSDV7 is asserted high when
port7 media is non_idle.
I Port7 RMII receive data bit_0.
I Port7 RMII receive data bit_1.
O Port7 RMII transmit enable signal.
O Port7 RMII transmit data bit_0.
O Port7 RMII transmit data bit_1.
I Port8 RMII receive interface signal, CRSDV8 is asserted high when
port8 media is non_idle.
I Port8 RMII receive data bit_0.
I Port8 RMII receive data bit_1.
O Port8 RMII transmit enable signal.
O Port8 RMII transmit data bit_0.
O Port8 RMII transmit data bit_1.
I Port9 RMII receive interface signal, CRSDV9 is asserted high when
port9 media is non_idle.
I Port9 RMII receive data bit_0.
I Port9 RMII receive data bit_1.
O Port9 RMII transmit enable signal.
O Port9 RMII transmit data bit_0.
O Port9 RMII transmit data bit_1.
I Port10 RMII receive interface signal, CRSDV10 is asserted high when
port10 media is non_idle.
I Port10 RMII receive data bit_0.
I Port10 RMII receive data bit_1.
O Port10 RMII transmit enable signal.
O Port10 RMII transmit data bit_0.
O Port10 RMII transmit data bit_1.
I Port11 RMII receive interface signal, CRSDV11 is asserted high when
port11 media is non_idle.
I Port11 RMII receive data bit_0.
I Port11 RMII receive data bit_1.
O Port11 RMII transmit enable signal.
O Port11 RMII transmit data bit_0.
O Port11 RMII transmit data bit_1.
5/27 MTD516 Revision 1.2 19/06/2000

5 Page





MTD516 arduino
MYSON
TECHNOLOGY
MTD516
(Preliminary)
4.0 FUNCTIONAL DESCRIPTIONS
The MTD516 is an 16 ports 10/100 Mbps fast Ethernet switch controller. It is a low cost solution for six-
teen ports fast Ethernet SOHO switch design. No CPU interface is required; After power on reset,
MTD516 provide an auto load configuration setting function through a 2 wire serial EEPROM interface
to acess external EEPROM device, and MTD516 can easily be configured to support port_trunking,
port_ VLAN, static entry, 802.3X flow control threshold setting , flooding port assignment ...etc func-
tions. The following descriptions are MTD516’s major functional blocks overview.
4.1 Packet store and forwarding
The MTD516 use simple store and forward algorithm as packet switching method. Input packet from
ports will be stored to external memory first, while packet is good for forward (CRC chech ok, 64Bytes <
length < 1518Bytes, not local packets, in the same VLAN group ) , if this packet’s DA hits, than forward
this packet to the destination port, otherwise this packet will be broadcasted.
4.2 Learning and Routing
The MTD516 supports 1K or 8K MAC entries for switching. Dynamic address learning is performed by
each good unicast packet is completely received. The static address learning is achieved by EEPROM
configuration. On the other hand, the routing process is performed whenever the packet’s DA is cap-
tured. If the DA can not get a hit result, the packet is going to switch broadcast or forward to the dedi-
cated port according to the flooding control selction.
4.3 Aging
Only the dynamic address entries are scheduled in the aging machine. If one station does not transmit
any packet for a period of time, the belonging MAC address will be kicked out from the address table.
The aging out time can be program through the EEPROM auto load configuration. (Default value is 300
seconds)
4.4 Buffer Queue Management
The buffer queue manager is implemented to manage the external shared memory (use SDRAM/
SGRAM) for packet buffering. The main function of the buffer queue manager is to maintain the linked
list consists of buffer IDs, which is used to show the corresponding memory address for each incoming
packet. In addition, the buffer queue manager monitors the rested free spaces status of the external
memory, If the packet storage achieve the predefined threshold value, the buffer queue manager will
raise the alarm signal which is used to enable the flow control mechanism for avoiding transmission ID
queue overflow happening. MTD516 provide 802.3x flow control in full duplex mode and back pressure
control in half duplex mode.
4.5 Full Duplex 802.3x Flow Control
In full duplex mode, MTD516 supports the standard flow control defined in IEEE802.3x standard. It
enables the stopping of remote node transmissions via a PAUSE frame information interactoin. When
the “802.3x flow control enable” bit is setted during power on reset (MDC pin is external pull_high),
it enables MTD516 supporting 802.3x flow control function in full_duplex mode; When output port buffer
queue’s on_using value reach the initialization setting threshold value(recommended XON_TH = 40’h
under total free ID less then 100’h), MTD516 will send out a PAUSE packet with pause time equal to
FFF to stop the remote node transmission; When the output port buffer queue’s on_using value reduce
to the initialization threshold value(recommended Xoff_TH = 1C’h when using 2Mbytes external mem-
ory), MTD516 will also send a PAUSE packet with pause time equal to zero to inform the remote node
to retransmit packet.
4.6 Half Duplex Back Pressure Control
In half duplex mode, MTD516 provide a back pressure control mechanism to avoid dropping packets
during network conjection situation. When the “back pressure control enable” bit is set during power on
11/27
MTD516 Revision 1.2 19/06/2000

11 Page







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