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PDF MTD502E Data sheet ( Hoja de datos )
| Número de pieza | MTD502E | |
| Descripción | 2 Port 10M/100M Switch | |
| Fabricantes | Myson | |
| Logotipo |  |
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MYSON
MTD502E
TECHNOLOGY
2 Port 10M/100M Switch With Build_in Memory
FEATURES
GENERAL DESCRIPTION
• IEEE802.3 and IEEE802.3u compliant.
• Single chip, low cost, two port switch controller.
• Build_in embedded memory on chip for packet
buffering.
• Provide 2 MII/RMII (Reduced Media Indepen-
dent Interface) ports.
• A flexible MII interface design can directly con-
nect with standard MII or pseudo MII.
• Support half/full duplex operation per port.
• Optional back_pressure control for half_duplex
mode.
• Provide “store and forward” switching, and for-
warding rate at full_wire speed.
• Support up to 2048 MAC addresses filtering
database, and automatical address aging_out
function (300 secs).
• Low power CMOS design, with single 3.3V
supply voltage, 50 MHZ operation.
• Provide 128 pin PQFP package (MTD502EF),
and 80 pin LQFP package (MTD502EG).
The MTD502E is a highly integrated, 10M/
100M two port switch controller with build_in
embedded memory. It supports 2 MII/RMII ports
for 10M/100M operation, and both can operate
under half or full duplex mode.
The MTD502E is an ideal solution for two
port bridge or dual speed hub application, and no
need any external memory buffers in application
design. The flexible MII interface design can
directly connect with pseudo MII interface
(Am79c901, HomePNA PHY).
The MTD502E provides packet forward-
ing, address filtering, learning, and aging func-
tion, and have an optional back_presure control
implemented in half duplex mode.
The MTD502E supports an effective
address filtering database, which can recognize
up to 2048 MAC addresses. It also support an
automatical aging function for address table
updating (aging time is 300 secs default).
BLOCK DIAGRAM
Two
Port
Switch
Engine
Port0 DMA
MAC0
MII0
Embedded Memory
Port1 DMA
MAC1
MII1
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification
without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of
the product.
1/20 MTD502E Revision 1.3 12/07/2000
1 page  
MYSON
TECHNOLOGY
MTD502E
2.0 PIN DESCRIPTIONS
MTD502EF (128PQFP) Pin Definition Mapping Under Different Configurations
Pin No. I/O
MII Phy_MII Rmii Phy_Rm
mode mode mode ii mode
Descriptions
1 I LINK0 (NC) LINK0 (NC) Pin 1~32 for Port0, suitable for connecting with 10/
100PHY , RISC_CPU, Switch,....
2 O TXD0_3 RXD0_3 (NC) (NC)
3 VCC
4 O TXD0_2 RXD0_2 (NC) (NC)
5 O (NC) CRS0 (NC) (NC)
6~8 I (NC) (NC) (NC) (NC)
9 O TXD0_1 RXD0_1 (NC) (NC)
10 O TXD0_0 RXD0_0 (NC) (NC)
11 O TXEN0 RXDV0 (NC) (NC)
12 I TXC0 (NC) (NC) (NC)
13 I (NC) (NC) (NC) (NC)
14 GND
15 I RXC0 (NC) CRSDV0 TXEN0
16 O (NC) RXC0 TXD0_1 RXD0_1
17 O (NC) COL0 TXD0_0 RXD0_0
18 O (NC) TXC0 TXEN0 CRSDV0
19 I RXD0_0 TXD0_0 RXD0_0 TXD0_0
20 I RXD0_1 TXD0_1 RXD0_1 TXD0_1
21 I FULL0 FULL0 FULL0 (NC)
22~24 O (NC) (NC) (NC) (NC)
25 I RXD0_2 TXD0_2 (NC) (NC)
26 I RXD0_3 TXD0_3 (NC) (NC)
27 I RXDV0 TXEN0 (NC) (NC)
28 I CRS0 SPEED0 SPEED0 (NC)
29 I COL0 (NC) (NC) (NC)
30 I SPEED0 (NC) (NC) (NC)
31 VCC
32 GND
33 I LINK1 (NC) LINK1 (NC) Pin 33~64 for Port1, suitable for connecting with
HomePNA PHY.
34 O TXD1_3 (NC) (NC) (NC)
35 O TXD1_2 (NC) (NC) (NC)
36 O (NC) (NC) (NC) (NC)
37,38
I (NC) (NC) (NC) (NC)
39 I (NC) (NC) CRSDV1 (NC)
40 O TXD1_1 (NC) TXD1_1 (NC)
41 O TXD1_0 (NC) TXD1_0 (NC)
42 O TXEN1 (NC) TXEN1 (NC)
43 I TXC1 (NC) RXD1_0 (NC)
44 I (NC) (NC) RXD1_1 (NC)
45 VCC
5/20 MTD502E Revision 1.3 12/07/2000
5 Page 
MYSON
TECHNOLOGY
MTD502E
3.0 MTD502EG (80LQFP) PIN DESCRIPTIONS
MTD502EG(80LQFP) Pin Definition Mapping Under Different Configurations
Pin No. I/O
1O
2O
3O
4O
5I
6 GND
7I
8O
9O
10 O
11 I
12 I
13 I
14 O
15 I
16 I
17 I
18 I
19 I
20 I
21 I
22 O
23 O
24 O
25 O
26 O
27 O
28 I
29 I
30 I
31 I
32 I
33 O
34 I
35 I
36 VCC
37 GND
38 I
39 I
MII
mode
(NC)
TXD0_1
TXD0_0
TXEN0
TXC0
RXC0
(NC)
(NC)
(NC)
RXD0_0
RXD0_1
FULL0
(NC)
RXD0_2
RXD0_3
RXDV0
CRS0
COL0
SPEED0
LINK1
TXD1_3
TXD1_2
(NC)
TXD1_1
TXD1_0
TXEN1
TXC1
RXC1
RXD1_0
RXD1_1
FULL1
(NC)
RXD1_2
RXD1_3
RXDV1
CRS1
Phy_MII
mode
CRS0
RXD0_1
RXD0_0
RXDV0
(NC)
Rmii
mode
(NC)
(NC)
(NC)
(NC)
(NC)
Phy_Rm
ii mode
Descriptions
(NC)
Pin 77~80, 1~20 for Port0, suitable for
connecting with 10/100PHY ,
RISC_CPU, Switch,....
(NC)
(NC)
(NC)
(NC)
(NC) CRSDV0 TXEN0
RXC0 TXD0_1 RXD0_1
COL0 TXD0_0 RXD0_0
TXC0 TXEN0 CRSDV0
TXD0_0 RXD0_0 TXD0_0
TXD0_1 RXD0_1 TXD0_1
FULL0 FULL0 (NC)
(NC) (NC) (NC)
TXD0_2 (NC) (NC)
TXD0_3 (NC) (NC)
TXEN0 (NC) (NC)
SPEED0 SPEED0 (NC)
(NC) (NC) (NC)
(NC) (NC) (NC)
(NC)
(NC)
(NC) Pin 21~41 for Port1, suitable for con-
necting with HomePNA PHY.
(NC) (NC) (NC)
(NC) (NC) (NC)
(NC) (NC) (NC)
(NC) (NC) (NC)
(NC) (NC) (NC)
(NC) (NC) (NC)
(NC) (NC) (NC)
(NC) (NC) (NC)
(NC) (NC) (NC)
(NC) (NC) (NC)
(NC) (NC) (NC)
(NC) (NC) (NC)
(NC) (NC) (NC)
(NC) (NC) (NC)
(NC)
(NC)
(NC)
(NC)
(NC)
(NC)
11/20
MTD502E Revision 1.3 12/07/2000
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MTD502E.PDF ] | |
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