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PDF AM79M574 Data sheet ( Hoja de datos )
| Número de pieza | AM79M574 | |
| Descripción | Metering Subscriber Line Interface Circuit | |
| Fabricantes | Legerity | |
| Logotipo |  |
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Am79M574
Metering Subscriber Line Interface Circuit
DISTINCTIVE CHARACTERISTICS
Programmable constant-resistance feed
Programmable loop-detect threshold
Ground-key detect
Performs polarity reversal
Line-feed characteristics independent of
battery variations
Test relay driver optional
Supports 2.2 Vrms metering (12 and 16 kHz)
On-chip switching regulator for low-power
dissipation
Two-wire impedance set by single external
impedance
Tip Open state for ground-start lines
On-hook transmission
BLOCK DIAGRAM
A(TIP)
Ring Relay Driver
Test Relay Driver
HPA
Two-Wire
Interface
Ground-Key
Detector
Input Decoder
and Control
HPB
Signal Transmission
Off-Hook Detector
B(RING)
DA
DB
VREG
L
VBAT
BGND
Power-Feed
Controller
Switching Regulator
Ring-Trip Detector
CHS QBAT CHCLK
VCC VEE AGND
Notes:
1. Am79M574—E0 and E1 inputs; ring and test relay drivers sourced internally to BGND.
2. Current gain (K1) = 1000.
RINGOUT
TESTOUT
C1
C2
C3
C4
E1
E0
DET
VTX
RSN
RD
RDC
16857C-001
Publication# 080135 Rev: E Amendment: /0
Issue Date: October 1999
1 page  
ABSOLUTE MAXIMUM RATINGS
Storage temperature . . . . . . . . . . . . –55°C to +150°C
VCC with respect to AGND/DGND . . .–0.4 V to +7.0 V
VEE with respect to AGND/DGND . . .+0.4 V to –7.0 V
VBAT with respect to AGND/DGND . . . +0.4 V to –70 V
Note: Rise time of VBAT (dv/dt) must be limited to 27 V/µs
or less when QBAT bypass = 0.33 µF.
BGND with respect to
AGND/DGND. . . . . . . . . . . . . . . .+1.0 V to –3.0 V
A(TIP) or B(RING) to BGND:
Continuous . . . . . . . . . . . . . . . . . –70 V to +1.0 V
10 ms (f = 0.1 Hz) . . . . . . . . . . . . –70 V to +5.0 V
1 µs (f = 0.1 Hz). . . . . . . . . . . . . . . –90 V to +10 V
250 ns (f = 0.1 Hz) . . . . . . . . . . . .–120 V to +15 V
Current from A(TIP) or B(RING). . . . . . . . . . . .±150 mA
Voltage on RINGOUT. . . . .BGND to 70 V above QBAT
Voltage on TESTOUT. . . . .BGND to 70 V above QBAT
Current through relay drivers . . . . . . . . . . . . . . 60 mA
Voltage on ring-trip inputs
(DA and DB) . . . . . . . . . . . . . . . . . . . . VBAT to 0 V
Current into ring-trip inputs . . . . . . . . . . . . . . . . .±10 mA
Peak current into regulator
switch (L pin) . . . . . . . . . . . . . . . . . . . . . . 150 mA
Switcher transient peak off
voltage on L pin . . . . . . . . . . . . . . . . . . . . . +1.0 V
C4–C1, E0, E1, CHCLK to
AGND/DGND. . . . . . . . . . . .–0.4 V to VCC + 0.4 V
Maximum power dissipation, (see note). . . .TA = 70°C
In 32-pin PLCC package . . . . . . . . . . . . . . 1.74 W
Note: Thermal limiting circuitry on chip will shut down the
circuit at a junction temperature of about 165°C. The de-
vice should never be exposed to this temperature. Opera-
tion above 145°C junction temperature may degrade
device reliability. See the SLIC Packaging Considerations
for more information.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient temperature . . . . . . . . . . . . . . .0°C to +70°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 V to 5.25 V
VEE . . . . . . . . . . . . . . . . . . . . . . . . –4.75 V to –5.25 V
VBAT. . . . . . . . . . . . . . . . . . . . . . . . . . . –40 V to –58 V
AGND/DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V
BGND with respect to
AGND/DGND . . . . . . . . . . . –100 mV to +100 mV
Load resistance on VTX to ground . . . . . . . 10 kΩ min
Operating Ranges define those limits between which the
functionality of the device is guaranteed.
* Functionality of the device from 0°C to +70°C is guaranteed
by production testing. Performance from –40°C to +85°C is
guaranteed by characterization and periodic sampling of
production units.
SLIC Products
5
5 Page 
Notes:
1. Unless otherwise noted, test conditions are BAT = –48 V, VCC = +5 V, VEE = –5 V, RL = 600 Ω, CHP = 0.22 µF,
RDC1 = RDC2 = 20 kΩ, CDC = 0.1 µF, Rd = 51.1 kΩ, no fuse resistors, two-wire AC output impedance, programming impedance
(ZT) = 306 kΩ resistive, receive input summing impedance (ZRX) = 300 kΩ resistive. (See Table 2 for
component formulas.)
2. Overload level is defined when THD = 1%.
3. Balance return signal is the signal generated at VTX by VRX. This specification assumes that the two-wire AC load impedance
matches the impedance programmed by ZT.
4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5. These tests are performed with a longitudinal impedance of 90 Ω and metallic impedance of 300 Ω for frequencies below
12 kHz and 135 Ω for frequencies greater than 12 kHz. These tests are extremely sensitive to circuit board layout.
6. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
7. When the SLIC is in the Anti-sat 2 operating region, this parameter is degraded. The exact degradation depends on system
design. The Anti-sat 2 region occurs at high loop resistances whenVBAT–VAX – VBXis less than approximately 17V.
8. "Midpoint" is defined as the connection point between two 300 Ω series resistors connected between A(TIP) and B(RING).
9. Fundamental and harmonics from 256 kHz switch-regulator chopper are not included.
10. Loop-current limit which depends upon the programmed apparent open circuit voltage and the feed resistance is calculated
as follows:
In OHT state:
ILIMIT = 0.5
-V----a--p---p--a--r--e--n--t
RFEED
In Active state: ILIMIT = 0.8
-V----a--p---p--a--r--e--n--t
RFEED
11. Total harmonic distortion with metering as specified with a metering signal of 2.2 Vrms at the two-wire output, and a transmit
signal of +3 dBm or receive signal of –4 dBm. The transmit or receive signals are single-frequency inputs, and the distortion
is measured as the highest in-band harmonic at the two-wire or the four-wire output relative to the input signal.
12. Noise with metering is measured by applying a 2.2 Vrms metering signal (measured at the two-wire output) and measuring
the psophometric noise at the two-wire and four-wire outputs over a 200 ms time interval.
13. Tested with 0 Ω source impedance. 2 MΩ is specified for system design purposes only.
14. Assumes the following ZT network:
VTX
153 kΩ
RSN
153 kΩ
56 pF
15. Group delay can be considerably reduced by using a ZT network such as that shown in Note 14. The network reduces the
group delay to less than 2 µs. The effect of group delay on linecard performance may be compensated for by using the
QSLAC™ or DSLAC™ devices.
State
0
1
2
3
4
5
6
7
C3 C2 C1
000
001
010
011
100
101
110
111
Table 1. SLIC Decoding
DET Output
Two-Wire Status
E0 = 1*
E1 = 0
E0 = 1*
E1 = 1
Open Circuit
Ring trip
Ring trip
Ringing
Ring trip
Ring trip
Active
Loop detector Ground key
On-hook TX (OHT)
Loop detector Ground key
Tip Open
Loop detector
—
Reserved
Loop detector
—
Active Polarity Reversal Loop detector Ground key
OHT Polarity Reversal Loop detector Ground key
Note:
* Logic Low on E0 disables the DET output into the open-collector state.
SLIC Products
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AM79M574.PDF ] | |
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