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PDF PLUS16L8D Data sheet ( Hoja de datos )

Número de pieza PLUS16L8D
Descripción PAL devices
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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Philips Semiconductors Programmable Logic Devices
PAL devices
16L8, 16R8, 16R6, 16R4
Product specification
PLUS16R8D/-7 SERIES
FEATURES
Ultra high-speed
tPD = 7.5ns and fMAX = 74MHz for the
PLUS16R8-7 Series
tPD = 10ns and fMAX = 60 MHz for the
PLUS16R8D Series
100% functionally and pin-for-pin
compatible with industry standard 20-pin
PAL® ICs
Power-up reset function to enhance state
machine design and testability
Design support provided via SNAP and
other CAD tools for Series 20 PAL devices
Field-programmable on industry standard
programmers
Security fuse
Individual 3-State control of all outputs
DESCRIPTION
The Philips Semiconductors PLUS16XX
family consists of ultra high-speed 7.5ns and
10ns versions of Series 20 PAL devices.
The PLUS16XX family is 100% functional
and pin-compatible with the 16L8, 16R8,
16R6, and 16R4 Series devices.
The sum of products (AND-OR) architecture
is comprised of 64 programmable AND gates
and 8 fixed OR gates. Multiple bidirectional
pins provide variable input/output pin ratios.
Individual 3-State control of all outputs and
registers with feedback (R8, R6, R4) is also
provided. Proprietary designs can be
protected by programming the security fuse.
The PLUS16R8, R6, and R4 have D-type
flip-flops which are loaded on the
Low-to-High transition of the clock input.
In order to facilitate state machine design and
testing, a power-up reset function has been
incorporated into these devices to reset all
internal registers to Active-Low after a
specific period of time.
The Philips Semiconductors State-of-the-Art
oxide isolation Bipolar fabrication process is
employed to achieve high-performance
operation.
The PLUS16XX family of devices are field
programmable, enabling the user to quickly
generate custom patterns using standard
programming equipment. See the
programmer chart for qualified programmers.
The SNAP software package from Philips
Semiconductors supports easy design entry
for the PLUS16XX series as well as other
PLD devices from Philips Semiconductors.
The PLUS16XX series are also supported by
other standard CAD tools for PAL-type
devices.
Order codes are listed in the Ordering
Information table.
DEVICE NUMBER
PLUS16L8
PLUS16R8
PLUS16R6
PLUS16R4
DEDICATED
INPUTS
10
8
8
8
COMBINATORIAL
OUTPUTS
8 (6 I/O)
0
2 I/O
4 I/O
REGISTERED
OUTPUTS
0
8
6
4
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
20-Pin Plastic Dual-In-Line
300mil-wide
PLUS16R8DN
PLUS16R6DN
PLUS16R4DN
PLUS16L8DN
PLUS16R8–7N
PLUS16R6–7N
PLUS16R4–7N
PLUS16L8–7N
20-Pin Plastic Leaded Chip Carrier (PLCC)
PLUS16R8DA
PLUS16R6DA
PLUS16R4DA
PLUS16L8DA
PLUS16R8–7A
PLUS16R6–7A
PLUS16R4–7A
PLUS16L8–7A
NOTE:
The PLUS16XX series of devices are also processed to military requirements for operation over
the military temperature range. For specifications and ordering information, consult the Philips
Semiconductors Military Data Book.
DRAWING NUMBER
0408B
0400E
®PAL is a registered trademark of Advanced Micro Devices, Inc.
September 10, 1993
36
853–1358 10777

1 page




PLUS16L8D pdf
Philips Semiconductors Programmable Logic Devices
PAL devices
16L8, 16R8, 16R6, 16R4
LOGIC DIAGRAM
CLK 1
0
I0 2
7
8
I1 3
15
16
I2 4
23
24
I3 5
31
32
I4 6
39
40
I5 7
47
48
I6 8
55
56
63
I7 9
0 INPUTS (0–31)
NOTES:
1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”.
2. Programmable connections.
Product specification
PLUS16R8D/-7 SERIES
PLUS16R8
DQ
Q
19 Q7
DQ
Q
18 Q6
DQ
Q
17 Q5
DQ
Q
16 Q4
DQ
Q
15 Q3
DQ
Q
14 Q2
DQ
Q
13 Q1
DQ
Q
12 Q0
11 OE
31
September 10, 1993
40

5 Page





PLUS16L8D arduino
Philips Semiconductors Programmable Logic Devices
PAL devices
16L8, 16R8, 16R6, 16R4
Product specification
PLUS16R8D/-7 SERIES
AC ELECTRICAL CHARACTERISTICS
R1 = 200, R2 = 390, 0°C Tamb +75°C, 4.75 VCC 5.25V
LIMITS
SYMBOL
PARAMETER
FROM
TO
–7
D UNIT
MIN1
TYP
MAX
MIN1
MAX
Pulse Width
tCKH
Clock High
tCKL
Clock Low
tCKP
Period
Setup & Hold time
CK+ CK– 5
CK– CK+ 5
CK+ CK+ 10
7 ns
7 ns
14 ns
tIS Input
Input or
feedback
CK+
7
9 ns
tIH Input
CK+
Input or
feedback
0
0 ns
Propagation delay
tCKO
tCKF
tPD
tOE1
tOE2
Clock
Clock3
Output (16L8, R6, R4)2
Output enable4
Output enable4,5
CK±
CK±
I, B
OE
I
Q±
Q
Output
Output enable
Output enable
3
3
3
3
6.5 3 7.5 ns
3 6.5 ns
7.5 3 10
ns
8 3 10 ns
10 3 10
ns
tOD1
Output disable4
OE
Output disable
3
8 3 10 ns
tOD2
Output disable4,5
I
Output disable
3
10 3 10
ns
tSKW
Output
QQ
1 1 ns
tPPR
Power-Up Reset
VCC+
Q+
10 10 ns
Frequency (16R8, R6, R4)
No feedback 1/ (tCKL + tCKH)6
100 71.4
MHz
fMAX
Internal feedback 1/ (tIS + tCKF)6
90 64.5 MHz
External feedback 1/ (tIS + tCKO)6
74 60.6 MHz
* For definitions of the terms, please refer to the Timing/Frequency Definitions tables.
NOTES:
1. CL = 0pF while measuring minimum output delays.
2. tPD test conditions: CL = 50pF (with jig and scope capacitance), VIH = 3V, VIL = 0V, VOH = VOL = 1.5V.
3. tCKF was calculated from measured Internal fMAX.
4. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output
voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed.
5. Same function as tOE1 and tOD1, with the difference of using product term control.
6. Not 100% tested, but calculated at initial characterization and at any time a modification in design takes place which may affect the
frequency.
September 10, 1993
46

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