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PDF CY2277A Data sheet ( Hoja de datos )
| Número de pieza | CY2277A | |
| Descripción | K6 Clock Synthesizer/Driver | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY2277A
Pentium®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/
Mobile PCs with Intel® 82430TX and 2 DIMMs or 3 SO-DIMMs
Features
• Mixed 2.5V and 3.3V operation
• Complete clock solution to meet requirements of Pen-
tium®, Pentium® II, 6x86, or K6 motherboards
— Four CPU clocks at 2.5V or 3.3V
— Up to eight 3.3V SDRAM clocks
— Seven 3.3V synchronous PCI clocks, one free
running
— Two 3.3V USB/IO clocks at 48 or 24 MHz, selectable
by serial interface
— One 2.5V IOAPIC clock at 14.318 MHz
— Two 3.3V Ref. clocks at 14.318 MHz
• Factory-EPROM programmable CPU, PCI, and USB/IO
clock frequencies for custom configuration
• Factory-EPROM programmable output drive and slew
rate for EMI customization
• MODE Enable pin for CPU_STOP and PCI_STOP
• SMBus serial configuration interface
• Available in space-saving 48-pin SSOP and TSSOP
packages.
Functional Description
The CY2277A is a Clock Synthesizer/Driver for Pentium, Pen-
tium II, 6X86, and K6 portable PCs designed with the Intel®
82430TX or similar chipsets. There are three available options
as shown in the selector guide
The CY2277A has power-down, CPU stop and PCI stop pins
for power management control. The CPU stop and PCI stop
are controlled by the MODE pin. They are multiplexed with
SDRAM clock outputs, and are selected when the MODE pin
is driven LOW. Additionally, these inputs are synchronized
on-chip, enabling glitch-free transitions. When the
CPU_STOP input is asserted, the CPU outputs are driven
LOW. When the PCI_STOP input is asserted, the PCI outputs
(except the free-running PCI clock) are driven LOW. Finally,
when the PWR_DWN pin is asserted, the reference oscillator
and PLLs are shut down, and all outputs are driven LOW.
The CY2277A outputs are designed for low EMI emission.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.
CY2277A Selector Guide
Clock Outputs
-1/-1M -3
-12/
-12M/
-7M -12I
CPU (60, 66.6 MHz) 4 -- 4 4
CPU (33.3, 66.6 MHz) -- 4 -- --
CPU (SMBus select-
--
--
--
--
able)
PCI (CPU/2)
7[1] 7[1] 7[1] 7[1]
SDRAM
6/8 6/8 6/8 6/8
The CY2277A outputs four CPU clocks at 2.5V or 3.3V with up
to nine selectable frequencies. There are up to eight 3.3V
SDRAM clocks and seven PCI clocks, running at one half the
CPU clock frequency. One of the PCI clocks is free-running.
Additionally, the part outputs two 3.3V USB/IO clocks at 48
MHz or 24 MHz, one 2.5V IOAPIC clock at 14.318 MHz, and
two 3.3V reference clocks at 14.318 MHz. The CPU, PCI,
USB, and IO clock frequencies are factory-EPROM program-
mable for easy customization with fast turnaround times.
USB/IO (48 or 24 MHz) 2
IOAPIC (14.318 MHz) 1
Ref (14.318 MHz)
2
CPU-PCI delay
1–6 ns
Note:
1. One free-running PCI clock.
2
1
2
1–6 ns
2
1
2
<1 ns
2
1
2
1–4 ns
Logic Block Diagram
XTALIN
XTALOUT
14.318
MHz
OSC.
CPU
PLL
STOP
LOGIC
SEL
MODE
PWR_DWN
SCLK
SDATA
EPROM
SYS
PLL
SERIAL
INTERFACE
CONTROL
LOGIC
/2
Delay
STOP
LOGIC
Divide and
Mux Logic
Pin Configuration
IOAPIC (14.318 MHz)
VDDQ2
REF [0–1]
(14.318)
CPUCLK[0–3]
REF1
REF0
VSS
XTALIN
XTALOUT
SSOP
Top View
1 48
2 47
3 46
4 45
5 44
AVDD
PWR_SEL
VDDQ2
IOAPIC
PWR_DWN
VDDCPU
SDRAM[0–5]
MODE
VDDQ3
PCICLK_F
PCICLK0
VSS
6
7
8
9
10
43 VSS
42 CPUCLK0
41 CPUCLK1
40 VDDCPU
39 CPUCLK2
SDRAM6/CPU_STOP
PCICLK1
PCICLK2
PCICLK3
11
12
13
38 CPUCLK3
37 VSS
36 SDRAM0
SDRAM7/PCI_STOP
PCICLK4
VDDQ3
PCICLK5
14
15
16
35 SDRAM1
34 VDDQ3
33 SDRAM2
VSS 17
32 SDRAM3
PCI[0–5]
PCICLK_F
SEL
SDATA
SCLK
18
19
20
31 VSS
30 SDRAM4
29 SDRAM5
VDDQ3
USBCLK/IOCLK[0:1] USBCLK/IOCLK
USBCLK/IOCLK
21
22
23
28 VDDQ3
27 SDRAM6/CPU_STOP
26 SDRAM7/PCI_STOP
VSS 24
25 AVDD
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07332 Rev. *A
Revised December 7, 2002
1 page  
CY2277A
Byte 1: CPU, 24/48 MHz Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit Pin #
Description
Bit 7 23
Bit 6 22
Bit 5 --
48/24 MHz (Active/Inactive)
48/24 MHz (Active/Inactive)
(Reserved) drive to ‘0’
Bit 4 N/A
Bit 3 38
Bit 2 39
Not Used, drive 0
CPUCLK3 (Active/Inactive)
CPUCLK2 (Active/Inactive)
Bit 1 41
Bit 0 42
CPUCLK1 (Active/Inactive)
CPUCLK0 (Active/Inactive)
Byte 3: SDRAM Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit Pin #
Description
Bit 7 26 SDRAM7 (Active/Inactive)
Bit 6 27 SDRAM6 (Active/Inactive)
Bit 5 29 SDRAM5 (Active/Inactive)
Bit 4 30 SDRAM4 (Active/Inactive)
Bit 3 32 SDRAM3 (Active/Inactive)
Bit 2 33 SDRAM2 (Active/Inactive)
Bit 1 35 SDRAM1 (Active/Inactive)
Bit 0 36 SDRAM0 (Active/Inactive)
Byte 5: Peripheral Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
--
--
--
45
--
--
1
2
Description
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
IOAPIC (Active/Inactive)
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
REF1 (Active/Inactive)
REF0 (Active/Inactive)
Byte 2: PCI Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit Pin #
Description
Bit 7 --
Bit 6 8
Bit 5 16
(Reserved) drive to ‘0’
PCICLK_F (Active/Inactive)
PCICLK5 (Active/Inactive)
Bit 4 14
Bit 3 13
Bit 2 12
PCICLK4 (Active/Inactive)
PCICLK3 (Active/Inactive)
PCICLK2 (Active/Inactive)
Bit 1 11
Bit 0 9
PCICLK1 (Active/Inactive)
PCICLK0 (Active/Inactive)
Byte 4: SDRAM Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Description
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Not used, drive to ‘0’
Byte 6: Reserved, for future use
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage ..................................................–0.5 to +7.0V
Input Voltage ............................................ –0.5V to VDD + 0.5
Storage Temperature (Non-Condensing) .... –65°C to +150°C
Junction Temperature............................................... +150°C
Package Power Dissipation.............................................. 1W
Static Discharge Voltage............................................ >2000V
(per MIL-STD-883, Method 3015, like VDD pins tied together)
Document #: 38-07332 Rev. *A
Page 5 of 19
5 Page 
CY2277A
Switching Characteristics (-12)[9, 10, 11]
Parameter Output
t1 All Clocks
t2 CPUCLK,
IOAPIC
Description
Output Duty Cycle[12]
CPU and IOAPIC Clock
Rising and Falling Edge
Rate
t2 PCI PCI Clock Rising and
Falling Edge Rate
t2
REF0
REF0 Clock Rising and
Falling Edge Rate
t2 SDRAM SDRAM Rising and Fall-
ing Edge Rate
t2
REF1
REF1, USB and IO Rising
USBCLK and Falling Edge Rate
IOCLK
t3 CPUCLK CPU Clock Rise Time
t3 USBCLK, USB Clock and I/O Clock
IOCLK
Rise Time
t4 CPUCLK CPU Clock Fall Time
t4 USBCLK, USB Clock and I/O Clock
IOCLK
Fall Time
t5 CPUCLK CPU-CPU Clock Skew
t6 CPUCLK, CPU-PCI Clock Skew
PCICLK (-12)
t7 CPUCLK, CPU-SDRAM Clock
SDRAM Skew
t8 CPUCLK Cycle-Cycle Clock Jitter
t8 PCICLK Cycle-Cycle Clock Jitter
t9 CPUCLK, Power-up Time
PCICLK,
SDRAM
t10 CPU, PCI, Frequency Slew Rate
SDRAM
Test Conditions
t1 = t1A ÷ t1B
Between 0.6V and 1.8V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
CPU clocks at 66.6 MHz
Between 0.4V and 2.4V, VDDCPU = 3.3V
Between 0.8V and 2.4V, VDDCPU = 3.3V
Between 0.5V and 2.0V
SDRAM clocks at 66.6 MHz
Between 0.4V and 2.4V
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
Between 0.4V and 2.4V
Between 2.0V and 0.4V, VDDCPU = 2.5V
Between 2.4V and 0.4V, VDDCPU = 3.3V
Between 2.4V and 0.4V
Measured at 1.25V, VDDCPU = 2.5V
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks, VDDCPU = 2.5V
Measured at 1.25V for 2.5V clocks and
at 1.5V for 3.3V clocks
Measured at 1.5V
CPU, PCI, and SDRAM clock stabiliza-
tion from power-up
Rate of change of frequency
Min.
45
1.0
1.0
1.0
1.0
1.5
0.5
0.4
0.4
1.0
0.4
0.4
1.0
1.0
Typ.
50
100
2
Max.
55
4.0
4.0
4.0
4.0
4.0
2.0
2.0
2.0
4.0
2.0
2.0
4.0
250
4.0
500
250
500
3
Unit
%
V/ns
V/ns
V/ns
V/ns
V/ns
ns
ns
ns
ns
ps
ns
ps
ps
ps
ms
MHz/
ms
Document #: 38-07332 Rev. *A
Page 11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet CY2277A.PDF ] | |
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