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PDF CY2273A Data sheet ( Hoja de datos )
| Número de pieza | CY2273A | |
| Descripción | K6 Clock Synthesizer/Driver | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY2273A
Pentium®/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs
with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs
Features
• Mixed 2.5V and 3.3V operation
• Complete clock solution for Pentium®, Pentium® II,
Cyrix, and AMD processor-based motherboards
— Four CPU clocks at 2.5V or 3.3V
— Up to twelve 3.3V SDRAM clocks
— Seven synchronous PCI clocks, one free-running
— One 3.3V 48 MHz USB clock
— One 2.5V IOAPIC clock (-3 option only)
— Two AGP clocks at 60 or 66.6MHz (-2 option only)
— One 3.3V Ref. clock at 14.318 MHz
• I2C™ Serial Configuration Interface
• Factory-EPROM programmable output drive and slew
rate for EMI customization
• Factory-EPROM programmable CPU clock frequencies
for custom configurations
• Power-down, CPU stop and PCI stop pins
• Available in space-saving 48-pin SSOP package
Functional Description
The CY2273A is a clock synthesizer/driver for a Pentium, Pen-
tium II, Cyrix, or AMD processor-based PC using Intel’s
82430TX, 82440LX, ALI Aladdin IV or Aladdin IV+ chipsets.
The CY2273A-1 outputs four CPU clocks at 2.5V or 3.3V with
up to 83.3MHz operation. There are seven PCI clocks, running
at 30 and 33.3MHz. One of the PCI clocks is free-running.
Additionally, the part outputs up to twelve 3.3V SDRAM clocks,
one 3.3V USB clock at 48 MHz, and one 3.3V reference clock
at 14.318 MHz. The CY2273A-2 is similar, except that
PCICLK4 and PCICLK5 are now AGP clocks. The CY2273A-3
is more suited to Pentium II systems, as it outputs one 2.5V
IOAPIC clock. Finally, the CY2273A-4 is similar to the
CY2273A-1 except that is supports 0-ns CPU-PCI delay.
The CY2273A possesses power-down, CPU stop, and PCI
stop pins for power management control. These inputs are
multiplexed with SDRAM clock outputs, and are selected when
the MODE pin is driven low. Additionally, the signals are syn-
chronized on-chip, and ensure glitch-free transitions on the
outputs. When the CPU_STOP input is asserted, the CPU
clock outputs are driven LOW. When the PCI_STOP input is
asserted, the PCI clock outputs (except the free-running PCI
clock) are driven LOW. When the PWR_DWN pin is asserted,
the reference oscillator and PLLs are shut down, and all out-
puts are driven LOW.
The CY2273A outputs are designed for low EMI emissions.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.
CY2273A Selector Guide
Clocks Outputs
-1
-2 -3 -4
CPU (60, 66.6, 75,
83.3 MHz)
CPU (60, 66.6 MHz)
4
--
4 -- 4
-- 4 --
SDRAM
PCI (30, 33.3MHz)
9/12
7[1]
9/12
5[1]
9/12
7[1]
9/12
7[1]
USB/IR (48MHz)
1 1 11
AGP (60 or 66MHz)
--
2 -- --
IOAPIC (14.318MHz)
--
-- 1 --
Ref (14.318MHz)
1 1 11
CPU-PCI delay
1–5.5 ns 1–5.5 ns
Note:
1. One free-running PCI clock.
0 ns
0 ns
Logic Block Diagram
XTALIN
XTALOUT
14.318
MHz
OSC.
CPU
PLL
STOP
LOGIC
CY2273A-3 only
IOAPIC
VDDQ2
REF0 (14.318 MHz)
CPUCLK [0-3]
VDDCPU
SEL0
SEL1
CY2273A-1,-2,-4 only
MODE
EPROM
SDRAM5/PWR_DWN
SDRAM [0-4],[8-11]
SDRAM6/CPU_STOP
Delay (-1,-2 option)
SYS PLL
SDRAM7/PCI_STOP
/1 or /1.25
/1 or /2
STOP
LOGIC
CY2273A-2 only
AGP [0,1]
PCI [0-5], PCI [0-3]
SCLK
SDATA
SERIAL
INTERFACE
CONTROL
LOGIC
PCICLK_F
USBCLK (48 MHz)
Intel and Pentium are registered trademarks of Intel Corporation. I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134
• 408-943-2600
October 12, 1998
1 page  
Byte 1: CPU Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
Description
47 (-1,-2, and -4) USBCLK
1 (-3 only)
N/A (Reserved) drive to ‘0’
N/A (Reserved) drive to ‘0’
N/A Not used - drive to ‘0’
40 CPUCLK3 (Active/Inactive)
41 CPUCLK2 (Active/Inactive)
43 CPUCLK1 (Active/Inactive)
44 CPUCLK0 (Active/Inactive)
Byte 3: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit Pin #
Description
Bit 7 28 SDRAM7 (Active/Inactive)
Bit 6 29 SDRAM6 (Active/Inactive)
Bit 5 31 SDRAM5 (Active/Inactive)
Bit 4 32
Bit 3 34
SDRAM4 (Active/Inactive)
SDRAM3 (Active/Inactive)
Bit 2 35 SDRAM2 (Active/Inactive)
Bit 1 37 SDRAM1 (Active/Inactive)
Bit 0 38 SDRAM0 (Active/Inactive)
Byte 5: Peripheral Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
N/A
N/A
N/A
47
N/A
N/A
N/A
2
Description
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
IOAPIC (Active/Inactive) (-3 only)
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
REF0 (Active/Inactive)
CY2273A
Byte 2: PCI Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
--
7
15
13
12
11
10
8
Description
(Reserved) drive to ‘0’
PCICLK_F (Active/Inactive)
PCICLK5 (Active/Inactive) (-1,-3 and -4)
AGP1 (Active/Inactive) (-2 only)
PCICLK4 (Active/Inactive) (-1,-3 and -4)
AGP0 (Active/Inactive) (-2 only)
PCICLK3 (Active/Inactive)
PCICLK2 (Active/Inactive)
PCICLK1 (Active/Inactive)
PCICLK0 (Active/Inactive)
Byte 4: SDRAM Active/Inactive Register
(1 = Active, 0 = Inactive), Default = Active
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Pin #
N/A
N/A
N/A
N/A
17
18
Description
Not used - drive to ‘0’
Not used - drive to ‘0’
Not used - drive to ‘0’
Not used - drive to ‘0’
SDRAM11
SDRAM10
Bit 1
Bit 0
20
21
SDRAM9
SDRAM8
Byte 6: Reserved, for future use
5
5 Page 
CY2273A
Switching Waveforms (continued)
CPU_STOP[11, 12]
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
CPU_STOP
CPUCLK
(External)
PCI_STOP[13, 14]
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
PCI_STOP
PCICLK
(External)
PWR_DOWN
CPUCLK
(Internal)
PCICLK
(Internal)
PWR_DWN
CPUCLK
(External)
PCICLK
(External)
VCO
Crystal
Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
Timing Requirements for the I2C Bus
SDA
SCL
t13 t20 t21
t14
t15
t18 t16
t19
Notes:
11. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles.
12. CPU_STOP may be applied asynchronously. It is synchronized internally.
13. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK.
14. PCI_STOP may be applied asynchronously. It is synchronized internally.
t17
t14
t22
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY2273A.PDF ] | |
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