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PDF LXP730 Data sheet ( Hoja de datos )
| Número de pieza | LXP730 | |
| Descripción | Multi-Rate DSL Framer | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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LXP730
Multi-Rate DSL Framer
Datasheet
The LXP730 is a multi-purpose Digital Subscriber Line (DSL) framer which complements the
Level One SK70725/21 Enhanced MDSL Data Pump (EMDP) to provide seamless transport of
data and voice signals over one or more DSL datapaths.
Applications
The LXP730 in combination with the EMDP
chipset is optimized for use as a framer or I/O
interface device for the following applications:
s Digital Pair Gain Systems
s Ethernet Modems
s T1/E1 Fractional Transport Systems
s Videoconferencing Systems
s Simultaneous Data - Voice Transport
Systems
s Wireless Base Station Access Systems
Product Features
The LXP730 provides the basic functions
required of a DSL framer:
s Synchronization of external data streams to
the DSL line
s Multiplexing and demultiplexing of
independent data streams for voice and data
s Loopback of payload data at the DSL
interface
s Creation, insertion, and recovery of the
MDSL Overhead (MOH) structure,
performance monitoring, and message
transport required in a DSL system with a
capacity of up to 32 kbps
s Supports two input/output data streams
simultaneously
— Slave mode: external clock determines
the rate at which data will be transferred
to and from the framer
— Master mode: clock derived from
received DSL clock or external
oscillator
s Single part architecture allows one chip to
be used economically in both central and
remote locations
s Supports systems with point-to-point
architectures
s Alternate Hardware Control mode (HWC)
for operation without an external
microprocessor
As of January 15, 2001, this document replaces the Level One document
LXP730 Multi-Rate DSL Framer Datasheet.
Order Number: 249266-001
January 2001
1 page  
Multi-Rate DSL Framer — LXP730
5.14
5.15
5.13.24 DX Z Bits 33 - 40 ....................................................................................68
5.13.25 DX Z Bits 41 - 48 ....................................................................................68
Reserved Registers (2 bytes)..............................................................................68
Interrupt Registers (2 bytes)................................................................................69
5.15.1 Interrupt Enables ....................................................................................69
5.15.2 Interrupt Status.......................................................................................69
6.0 Mechanical Specifications....................................................................................70
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
LXP730 Block Diagram ......................................................................................... 9
LXP730 Pin Assignments....................................................................................10
Clock Generation and Distribution.......................................................................22
Frame Format for N=12.......................................................................................26
Activation State Machine.....................................................................................27
High Performance Voice/Data Transport ............................................................28
Pair Gain Transport .............................................................................................29
T1/E1 Fractional Transport..................................................................................29
IOM Adaption Circuitry ........................................................................................30
Multiple Interrupt Line Circuit...............................................................................32
Generic PCM Interface Timing ............................................................................34
PCM Timing, 1X Clock ........................................................................................35
PCM Timing, 2X Clock ........................................................................................36
Codec Interface Timing .......................................................................................37
Asynchronous Port Timing ..................................................................................38
OSIO Timing........................................................................................................39
MDSL Interface Input Timing...............................................................................40
MDSL Interface Output Timing............................................................................40
E1/T1 Input Timing ..............................................................................................41
E1/T1 Output Timing ...........................................................................................41
Microprocessor Write Cycle - Motorola Mode .....................................................42
Microprocessor Read Cycle - Motorola Mode .....................................................43
Microprocessor Write Cycle - Intel Mode ............................................................44
Microprocessor Read Cycle - Intel Mode ............................................................45
Reset Timing .......................................................................................................45
64 - Pin LQFP Package Specification .................................................................70
Datasheet
5
5 Page 
Multi-Rate DSL Framer — LXP730
Table 1. LXP730 Pin Descriptions
Pin Symbol Type1
Description
1, 9, 16,
33, 48
VCC
_ Power Supply.
10, 17,
32, 49,
64
GND
_ Ground.
28
DATA0/
CRC_ERROR
DI/O, DO
DATA0. MPC mode/CRC_ERROR. flag HWC mode, indicates an error was detected
in the previous frame.
29
DATA1/FEBE
DI/O, DO
DATA1. MPC mode/FEBE. flag HWC mode, indicates the other side of the DSL link
encountered a CRC error.
30
DATA2/
LINK_ACTIVE
DI/O, DO
DATA2. MPC mode/LINK_ACTIVE. HWC mode, indicates that the DSL link is active
and ready to transport data.
31
DATA3/RUN-
STOP
DI/O, DI
DATA3. MPC mode/RUN-STOP. HWC mode, set to low to activate the DSL link,
edge triggered input.
34
DATA4/
FRMSYNC15
DI/O, DO DATA4. MPC mode /FRMSYNC15. HWC mode, Frame Sync Pulse, channel 15.
35
DATA5/
FRMSYNC16
DI/O, DO DATA5. MPC mode /FRMSYNC16. HWC mode. Frame Sync Pulse, channel 16.
36
DATA6/
FRMSYNC17
DI/O, DO DATA6. MPC mode /FRMSYNC17. HWC mode. Frame Sync Pulse, channel 17.
37
DATA7/
FRMSYNC18
DI/O, DO DATA7. MPC mode /FRMSYNC18. HWC mode. Frame Sync Pulse, channel 17.
22
ADDR0/
FRMSYNC13
DI, DO
ADDR0. MPC mode/FRMSYNC13. HWC mode. Frame Sync Pulse, channel 13,
output.
23 ADDR1/N1
DI ADDR1. MPC mode/N1. DSL rate select, HWC mode.
24 ADDR2/N2
DI ADDR2. MPC mode/N2. DSL rate select, HWC mode.
25 ADDR3/N3
DI ADDR3. MPC mode/N3. DSL rate select, HWC mode.
26 ADDR4/N4
DI ADDR4. MPC mode/N4. DSL rate select, HWC mode.
27
ADDR5/
FRMSYNC14
DI, DO
ADDR5. MPC mode/FRMSYNC14. Frame Sync Pulse, channel 14, output, HWC
mode.
57 MOTEL/HWC
DI
MOTEL/HWC. Set high for Motorola mode, set low for Intel mode, Micro Processor
Control (MPC) mode, input /HWC. pull high for HWC mode, input.
39
R/W(WR)/HWC
select
DI
R/W(WR). R/W for Motorola interface, WR for Intel interface /HWC select, set low for
HWC mode.
40 (RD)/HWC select
DI
(RD). Unused for Motorola interface, RD for Intel interface /HWC select, set low for
HWC mode.
38 CS /HWC select
DI CS. Chip select, HWC select, set low for HWC mode.
41 ALE/HTU_SEL
DI
ALE. Address latch enable for Intel interface, MPC mode, input /HTU_SEL. HTUC/
HTUR select, High for HTUC, Low for HTUR, HWC mode, input.
1. AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; NC = No Clamp. Pad will not clamp input in
the absence of power; PU = Input contains pull-up; PD = Input contains pull-down; I/O = Input/Output; OD = Open Drain
Output;
TO = Tri-State Output.
Datasheet
11
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