PDF CY7C1380CV25 Data sheet ( Hoja de datos )

Número de pieza	CY7C1380CV25
Descripción	(CY7C1380CV25 / CY7C1382CV25) 512K x 36/1M x 18 Pipelined SRAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! 380C V25 www.DataSheet4U.com PRELIMINARY CY7C1380CV25 CY7C1382CV25 512K x 36/1M x 18 Pipelined SRAM Features • Fast clock speed: 250, 225, 200, 167 MHz • Provide high-performance 3-1-1-1 access rate • Fast OE access times: 2.6, 2.8, 3.0, 3.4 ns • Optimal for depth expansion • Single 2.5V ±5% power supply • Common data inputs and data outputs • Byte Write Enable and Global Write control • Chip enable for address pipeline • Address, data, and control registers • Internally self-timed Write cycle • Burst control pins (interleaved or linear burst sequence) • Automatic power-down available using ZZ mode or CE deselect • Available in 119-ball bump BGA, 165-ball FBGA and 100-pin TQFP packages • JTAG boundary scan for BGA packaging version Functional Description The Cypress Synchronous Burst SRAM family employs high- speed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors. The CY7C1382CV25 and CY7C1380CV25 SRAMs integrate 1,048,576x18 and 524,288x36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for inter- nal burst operation. All synchronous inputs are gated by reg- isters controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE), burst control in- puts (ADSC, ADSP, and ADV), write enables (BWa, BWb, BWc, BWd and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and burst mode control (MODE). The data (DQa,b,c,d) and the data par- ity (DQPa,b,c,d) outputs, enabled by OE, are also asynchro- nous. DQa,b,c,d and DPa,b,c,d apply to CY7C1380CV25 and DQa,b and DPa,b apply to CY7C1382CV25. a, b, c, d each are of 8 bits wide in the case of DQ and 1 bit wide in the case of DP. Addresses and chip enables are registered with either address status processor (ADSP) or address status controller (ADSC) input pins. Subsequent burst addresses can be internally gen- erated as controlled by the burst advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the write control inputs. Indi- vidual byte write allows individual byte to be written. BWa con- trols DQa and DPa. BWb controls DQb and DPb. BWc controls DQc and DPd. BWd controls DQd and DPd. BWa, BWb BWc, and BWd can be active only with BWE being LOW. GW being LOW causes all bytes to be written. Write pass-through capa- bility allows written data available at the output for the next Read cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. All inputs and outputs of the CY7C1380CV25 and the CY7C1382CV25 are JEDEC standard JESD8-5 compatible. Selection Guide 250 MHz 225 MHz 200 MHz 167 MHz Unit Maximum Access Time 2.6 2.8 3.0 3.4 ns Maximum Operating Current 350 325 300 275 mA Maximum CMOS Standby Current 70 70 70 70 mA Shaded areas contain advance information. Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-05240 Rev. A Revised November 20, 2002 1 page PRELIMINARY Pin Configurations (continued) CY7C1380CV25 CY7C1382CV25 165-Ball Bump FBGA CY7C1380CV25 (512K x 36) - 11 x 15 FBGA 12 A NC A B NC C DPc A NC D DQc DQc E DQc DQc F DQc DQc G DQc DQc H NC VSS J DQd DQd K DQd DQd L DQd DQd M DQd DQd N DPd NC P NC 72M R MODE 36M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A 11 NC 144M DPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DPa A A CY7C1382CV25 (1M x 18) - 11 x 15 FBGA 1 A NC 2 A B NC A C NC NC D NC DQb E NC DQb F NC DQb G NC DQb H NC J DQb VSS NC K DQb L DQb NC NC M DQb NC N DPb NC P NC 72M R MODE 36M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A 11 A 144M DPa DQa DQa DQa DQa ZZ NC NC NC NC NC A A Document #: 38-05240 Rev. A Page 5 of 33 5 Page PRELIMINARY Write Cycle Descriptions[1, 5, 6] Function (1380CV25) Read Read Write Byte 0 – DQa Write Byte 1 – DQb Write Bytes 1, 0 Write Byte 2 – DQc Write Bytes 2, 0 Write Bytes 2, 1 Write Bytes 2, 1, 0 Write Byte 3 – DQd Write Bytes 3, 0 Write Bytes 3, 1 Write Bytes 3, 1, 0 Write Bytes 3, 2 Write Bytes 3, 2, 0 Write Bytes 3, 2, 1 Write All Bytes Write All Bytes GW BWE 11 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 0X BWd X 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 X CY7C1380CV25 CY7C1382CV25 BWc X 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 X BWb X 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 X BWa X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X Function (1382CV25) Read Read Write Byte 0 – DQ[7:0] and DP0 Write Byte 1 – DQ[15:8] and DP1 Write All Bytes Write All Bytes GW BWE BWb BWa 1 1 XX 10 11 10 10 10 01 10 00 0 X XX Notes: 5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWx. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a “don't care” for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ = High-Z when OE is inactive or when the device is deselected, and DQ = data when OE is active. Document #: 38-05240 Rev. *A Page 11 of 33 11 Page

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