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PDF LAN91C110 Data sheet ( Hoja de datos )
| Número de pieza | LAN91C110 | |
| Descripción | FEAST FAST ETHERNET CONTROLLER | |
| Fabricantes | SMSC Corporation | |
| Logotipo |  |
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LAN91C110 REV. B
PRELIMINARY
FEAST Fast Ethernet Controller
for PCMCIA and Generic 16-Bit Applications
FEATURES
Dual Speed CSMA/CD Engine (10 Mbps and 100
Mbps)
Compliant with IEEE 802.3 100BASE-T
Specification
Supports 100BASE-TX, 100BASE-T4
16 Bit Wide Data Path (into Packet Buffer Memory)
Generic 16-bit System Level Interface Easily
Adaptable to ISA, PCMCIA (16-bit CardBus), and
Various CPU System Interfaces
Support for 16 and 8 Bit CPU Accesses
Asynchronous Bus Interface
128 Kbyte External Memory
Built-in Transparent Arbitration for Slave Sequential
Access Architecture
Early TX, Early RX Functions
Flat MMU Architecture with Symmetric Transmit
and Receive Structures and Queues
IEEE-802.3 MII (Media Independent Interface)
Compliant MAC-PHY Interface Running at Nibble
Rate
MII Management Serial Interface
IEEE-802.3u Full Duplex Capability
144 Pin TQFP Package (1.0 Millimeter Height)
GENERAL DESCRIPTION
The LAN91C110 is designed to facilitate the implementation of second generation Fast Ethernet PC Card adapters and
other non-PCI connectivity products. The LAN91C110 is a digital device that implements the Media Access Control (MAC)
portion of the CSMA/CD protocol at 10 and 100 Mbps, and couples it with a lean and fast data and control path system
architecture to ensure that the CPU to packet RAM data movement does not cause a bottleneck at 100 Mbps.
The LAN91C110 implements a generic 16-bit host interface which is adaptable to a wide range of system buses and
CPUs. This makes the LAN91C110 ideal for 10/100 Fast Ethernet implementations in systems based on system buses
other than PCI.
Total memory size is 128 Kbytes, equivalent to a total chip storage (transmit plus receive) of 64 outstanding packets. The
LAN91C110 is software compatible with the LAN9000 family of products in the default mode and can use existing
LAN9000 drivers (ODI, IPX, and NDIS) with minor modifications in 16 and 32 bit Intel X86 based environments.
Memory management is handled using a unique patented MMU (Memory Management Unit) architecture and an
internal 32-bit wide data path. This I/O mapped architecture can sustain back-to-back frame transmission and
reception for superior data throughput and optimal performance. It also dynamically allocates buffer memory in an
efficient buffer utilization scheme, reducing software tasks and relieving the host CPU from performing these
housekeeping functions. The total memory size is 128 Kbytes (external), equivalent to a total chip storage (transmit
and receive) of 64 outstanding packets.
FEAST provides a flexible slave interface for easy connectivity with industry-standard buses. The host interface is
“ISA-like” and is easily adapted to a wide range of system and CPU buses such as ISA, PCMCIA, etc.
An IEEE-802.3 compliant Media Independent Interface (MII) provided on the network side of the LAN91C110. The MII
interface allows the use of a wide range of MII compliant Physical Layer (PHY) devices to be used with the LAN91C110.
The LAN91C110 also provides an interface to the two-line MII serial management protocol.
SMSC DS – LAN91C110 REV. B
Page 1
Rev. 09/05/02
1 page  
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
TABLE 1 - DESCRIPTION OF PIN FUNCTIONS
144 TQFP
PIN NO.
115-112,
110-100
138
118, 117
NAME
Address
Address
Enable
SYMBOL
A[15:1]
AEN
nBE[1:0]
89, 91-95, Data Bus
97-98, 119,
121-123,
125-128
135 Reset
D[15:0]
RESET
129 Asynchro- ARDY
nous
Ready
120 Local
nLDEV
Device
88 nAddress nADS
Strobe
131 Interrupt INTR0
132
134
56-57, 60-
65, 46-48,
50-54, 35-
38, 40-42,
45, 25-28,
30-32, 34
nRead nRD
Strobe
nWrite nWR
Strobe
RAM Data RD[31:0]
Bus
BUFFER
TYPE
I
I
I
I/O8
IS
OD16
O16
IS
O4
IS
DESCRIPTION
Input. Used by LAN91C110 for internal register
selection.
Input. Used as an address qualifier. Address
decoding is only enabled when AEN is low.
Input. Used during LAN91C110 register accesses
to determine the width of the access and the
register(s) being accessed.
Bidirectional. 16-bit data bus used to access the
LAN91C110’s internal registers. Data bus has
weak internal pullups. Supports direct connection
to the system bus without external buffering.
Input. This input is not considered active unless it
is active for at least 100ns to filter narrow glitches.
Open drain output. ARDY may be used when
interfacing asynchronous buses to extend
accesses. Its rising (access completion) edge is
controlled by the XTAL1 clock and, therefore,
asynchronous to the host CPU or bus clock.
Note: Asserted for 100 to 150ns for the
appropriate NO WAIT bit state in the Configuration
register. See the NO WAIT bit description for
complete information.
Output. Local Device. This active low output is
asserted when AEN is low and A4-A15 decode to
the LAN91C110 address programmed into the
high byte of the Base Address Register. nLDEV*
is a combinatorial decode of unlatched address
and AEN signals.
Input. Address strobe. For systems that require
address latching. The rising edge of nADS
indicates the latching moment of A[1:15] and AEN.
All LAN91C110 internal functions of A[1:15] and
AEN are latched.
Output. The interrupt output is enabled by
selecting the appropriate routing bits (INT SEL 1-
0) in the Configuration Register.
Input. Used in asynchronous bus interfaces.
IS Input. Used in asynchronous bus interfaces.
I/O4 with
pullups
Bidirectional. Carries the local buffer memory
read and write data. Reads are always 32 bits
wide. Writes are controlled individually at the byte
level.
SMSC DS – LAN91C110 REV. B
Page 5
Rev. 09/05/02
5 Page 
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
RX_ER might be asserted during packet reception to signal the LAN91C110 that the present receive packet is invalid. The
LAN91C110 will discard the packet by treating it as a CRC error.
RXD0-RXD3 should always be aligned to packet nibbles, therefore, opening flag detection does not consider misaligned
cases. Opening flag detection expects the 5Dh pattern and will not reject the packet on non-preamble patterns.
CRS100 is used as a frame envelope signal for the CSMA/CD MAC state machines (deferral and backoff functions), but it
is not used for receive framing functions. CRS100 is an asynchronous signal and it will be active whenever there is activity
on the cable, including LAN91C110 transmissions and collisions.
The MII SELECT bit in the CONFIG REGISTER must always be set for proper chip function.
Note that given the modular nature of the MII, TX25 and RX25 cannot be assumed to be free running clocks. The
LAN91C110 will not rely on the presence of TX25 and RX25 during reset and will use its own internal clock whenever a
timeout on TX25 is detected.
MII Management Interface Block
PHY management through the MII management interface is supported by the LAN91C110 by providing the means to
drive a tri-statable data output, a clock, and reading an input. Timing and framing for each management command is to be
generated by the CPU.
SMSC DS – LAN91C110 REV. B
Page 11
Rev. 09/05/02
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LAN91C110.PDF ] | |
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