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PDF NET2890 Data sheet ( Hoja de datos )

Número de pieza NET2890
Descripción USB Interface Controller
Fabricantes NetChip　
Logotipo NetChip Logotipo



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No Preview Available ! NET2890 Hoja de datos, Descripción, Manual

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NetChip
Technology, Inc.
335 Pioneer Way
Mt View, California 94041
(650) 526-1490 Fax (650) 526-1494
e-mail: [email protected]
Internet: www.netchip.com
NET2890 USB Interface Controller
Specification
For Revision 2 IC
Doc #: 605-0057-0209
Revision: 2.0 Draft 9
Date: 7/16/99

1 page




NET2890 pdf
Specification
NET2890 USB Interface Controller
5.6.8
5.6.9
5.6.10
5.6.11
5.6.12
5.6.13
5.6.14
5.6.15
5.6.16
5.6.17
5.6.18
5.6.19
5.6.20
5.6.21
5.6.22
5.6.23
5.6.24
5.6.25
5.6.26
5.6.27
(Index 10h; EP0PKTSIZLSB) EP0 Max Packet Size (LSB) .................................................. 52
(Index 12h; EPAPKTSIZLSB) EPA Max Packet Size (LSB) ................................................. 52
(Index 13h; EPAPKTSIZMSB) EPA Max Packet Size (MSB) ............................................... 52
(Index 14h; EPBPKTSIZLSB) EPB Max Packet Size (LSB) ................................................. 52
(Index 15h; EPBPKTSIZMSB) EPB Max Packet Size (MSB) ............................................... 53
(Index 16h; EPCPKTSIZLSB) EPC Max Packet Size (LSB)................................................. 53
(Index 17h; EPCPKTSIZMSB) EPC Max Packet Size (MSB)............................................... 53
(Index 18h; EPDPKTSIZLSB) EPD Max Packet Size (LSB) ................................................ 53
(Index 19h; EPDPKTSIZMSB) EPD Max Packet Size (MSB) .............................................. 53
(Index 20h; F0_AETH) FIFO 0 Almost Empty Threshold Register...................................... 53
(Index 22h; F0_AFTH) FIFO 0 Almost Full Threshold Register ......................................... 54
(Index 24h; FA_AETH) FIFO A Almost Empty Threshold Register ..................................... 54
(Index 26h; FA_AFTH) FIFO A Almost Full Threshold Register ........................................ 54
(Index 28h; FB_AETH) FIFO B Almost Empty Threshold Register ..................................... 54
(Index 2Ah; FB_AFTH) FIFO B Almost Full Threshold Register ........................................ 54
(Index 2Ch; FC_AETH) FIFO C Almost Empty Threshold Register .................................... 54
(Index 2Eh; FC_AFTH) FIFO C Almost Full Threshold Register........................................ 54
(Index 30h; FD_AETH) FIFO D Almost Empty Threshold Register .................................... 55
(Index 32h; FD_AFTH) FIFO D Almost Full Threshold Register........................................ 55
(Index FFh; REVISION) Revision Register .......................................................................... 55
6. STANDARD DEVICE REQUESTS .................................................................................................. 56
6.1 CONTROL ‘READ’ TRANSFERS ....................................................................................................... 57
6.1.1 Get Device Status .................................................................................................................. 57
6.1.2 Get Interface Status............................................................................................................... 57
6.1.3 Get Endpoint Status .............................................................................................................. 57
6.1.4 Get Device Descriptor (18 Bytes) ......................................................................................... 57
6.1.5 Get Configuration Descriptor (55 bytes) .............................................................................. 58
6.1.6 Get String Descriptor 0......................................................................................................... 60
6.1.7 Get String Descriptor 1......................................................................................................... 60
6.1.8 Get String Descriptor 2......................................................................................................... 61
6.1.9 Get Configuration ................................................................................................................. 61
6.1.10 Get Interface ......................................................................................................................... 61
6.2 CONTROL ‘WRITE’ TRANSFERS ..................................................................................................... 61
6.2.1 Set Address............................................................................................................................ 61
6.2.2 Set Configuration .................................................................................................................. 61
6.2.3 Set Interface .......................................................................................................................... 61
6.2.4 Device Clear Feature............................................................................................................ 62
6.2.5 Device Set Feature ................................................................................................................ 62
6.2.6 Endpoint Clear Feature ........................................................................................................ 62
6.2.7 Endpoint Set Feature ............................................................................................................ 62
7. ELECTRICAL SPECIFICATIONS.................................................................................................. 63
7.1 ABSOLUTE MAXIMUM RATINGS..................................................................................................... 63
7.2 RECOMMENDED OPERATING CONDITIONS ..................................................................................... 63
7.3 DC SPECIFICATIONS....................................................................................................................... 64
7.3.1 Core DC Specifications......................................................................................................... 64
7.3.2 USB Port DC Specifications ................................................................................................. 64
7.3.3 Local Bus (+3.3V) DC Specifications ................................................................................... 65
7.3.4 Local Bus (+5.0V) DC Specifications ................................................................................... 65
7.4 AC SPECIFICATIONS....................................................................................................................... 66
7.4.1 USB Port AC Specifications.................................................................................................. 66
7.4.2 USB Port AC/DC Specification Notes................................................................................... 67
7.4.3 USB Port AC Waveforms ...................................................................................................... 67
____________________________________________________________________________________
NetChip Technology, Inc., 1999
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
Rev 2.0, Draft 9, July 16, 1999
5

5 Page





NET2890 arduino
Specification
NET2890 USB Interface Controller
PKTLENLSB
• Moved from Index register 5 to Base register 0Bh.
PKTLENMSB
• Moved from Index register 6 to Base register 0Ch.
FIFOBASE
• Register is obsolete.
FIFOSIZE
• Register is obsolete. FIFOs are all fixed sizes.
FIFOCTL
• Moved to Endpoint paged registers address 1Ch.
• “Fifo Enable” bit, “Endpoint Select”bits are obsolete.
• FIFO Valid Bit removed, moved to FIFOSTAT.
FIFOINTENB
• Removed. Interrupt enables moved to EPIRQENB register.
FIFOSTAT
• Moved to Endpoint registers address 1Eh.
• “FIFO Valid” bit added, changed to Yes/SET with Auto-Clear feature.
• FIFO Almost Full and Almost Empty interrupts moved to EPIRQSTAT register.
FIFOCNT
• Moved to Endpoint paged registers address 1Ah.
EPRSPSET
• “Zero-Length Packet Response” bit is obsolete.
• “Endpoint Stall” and “Endpoint Toggle” bits have been swapped. See the description in
Section 5, Registers.
EPRSPCLR
• “Zero-Length Packet Response” bit is obsolete.
• “Endpoint Stall” and “Endpoint Toggle” bits have been swapped. See the description in
Section 5, Registers.
EPIRQENB
• Bits have been re-arranged to simplify software. See Section 5, Registers.
EPUSBSTAT
• Transmit Register Valid, Receive Register Valid bits are obsolete.
• “Timeout” status bit and Short Packet Transferred added.
IRQENB2
• FIFO interrupt enables moved to EPIRQENB register.
INDEX2
• Removed.
MINDEX1
• Removed.
MINDEX2
• Removed.
DIAG
• Added new index register to control diagnostic features.
EPnPKTSIZE
• Added new maximum packet size registers (Index 10h to 19h).
FIFOETHRS
• Renamed Fn_AETH. The FIFO almost empty threshold registers have been moved from
the Endpoint/FIFO registers to the index registers.
FIFOFTHRS
• Renamed Fn_AFTH. The FIFO almost full threshold registers have been moved from the
Endpoint/FIFO registers to the index registers.
____________________________________________________________________________________
NetChip Technology, Inc., 1999
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
Rev 2.0, Draft 9, July 16, 1999
11

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