PDF ISP1016E Data sheet ( Hoja de datos )

Número de pieza	ISP1016E
Descripción	High-Density Programmable Logic
Fabricantes	Lattice Semiconductor
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No Preview Available ! www.DataSheet4U.com ispLSI® and pLSI® 1016E High-Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic • HIGH-PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • ispLSI OFFERS THE FOLLOWING ADDED FEATURES — In-System Programmable™ (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Device for Faster Prototyping • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • pLSI/ispLSI DEVELOPMENT TOOLS pDS® Software — Easy to Use PC Windows™ Interface — Boolean Logic Compiler — Manual Partitioning — Automatic Place and Route — Static Timing Table ispDS+™ Software — Industry Standard, Third-Party Design Environments — Schematic Capture, State Machine, HDL — Automatic Partitioning and Place and Route — Comprehensive Logic and Timing Simulation — PC and Workstation Platforms A0 A1 D Q A2 D Q Logic A3 Array D Q GLB A4 DQ A5 A6 A7 Global Routing Pool (GRP) B7 B6 B5 B4 B3 B2 B1 B0 CLK Description 0139C1-isp The ispLSI and pLSI 1016E are High-Density Programmable Logic Devices containing 96 Registers, 32 Universal I/O pins, four Dedicated Input pins, three Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016E features 5-Volt in-system programming and in-system diagnostic capabilities. The ispLSI 1016E offers non-volatile “on-the-fly” reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. It is architecturally and parametrically compatible to the pLSI 1016E device, but multiplexes four input pins to control in-system programming. A functional superset of the ispLSI and pLSI 1016 architecture, the ispLSI and pLSI 1016E devices add a new global output enable pin. The basic unit of logic on the ispLSI and pLSI 1016E devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...B7 (see figure 1). There are a total of 16 GLBs in the ispLSI and pLSI 1016E devices. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com February 1997 1996 ISP Encyclopedia 1016E_04 1 page Specifications ispLSI and pLSI 1016E External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST 4 COND. #2 DESCRIPTION1 -125 -100 -80 UNITS MIN. MAX. MIN. MAX. MIN. MAX. tpd1 A 1 Data Prop. Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 – 15.0 ns tpd2 A 2 Data Prop. Delay, Worst Case Path – 10.0 – 13.0 – 18.5 ns fmax A 3 Clk. Frequency with Int. Feedback3 125 – 100 – 84.0 – MHz fmax (Ext.) – 4 Clk. Frequency with Ext. (Feedback 1 tsu2 + )tco1 100 – 77 – 57.0 – MHz fmax (Tog.) – 5 Clk. Frequency, Max. Toggle( 1 twh + )tw1 167 – 125 – 100 – MHz tsu1 – 6 GLB Reg. Setup Time before Clk., 4 PT Bypass 5.0 – 7.0 – 8.5 – ns tco1 A 7 GLB Reg. Clk. to Output Delay, ORP Bypass – 4.5 – 5.0 – 8.0 ns th1 – 8 GLB Reg. Hold Time after Clk., 4 PT Bypass 0.0 – 0.0 – 0.0 – ns tsu2 – 9 GLB Reg. Setup Time before Clk. 5.5 – 8.0 – 9.5 – ns tco2 – 10 GLB Reg. Clk. to Output Delay – 5.5 – 6.0 – 9.5 ns th2 – 11 GLB Reg. Hold Time after Clk. 0.0 – 0.0 – 0.0 – ns tr1 A 12 Ext. Reset Pin to Output Delay – 10.0 – 13.5 – 17.0 ns trw1 – 13 Ext. Reset Pulse Duration 5.0 – 6.5 – 10.0 – ns tptoeen B 14 Input to Output Enable – 12.0 – 15.0 – 20.0 ns tptoedis C 15 Input to Output Disable – 12.0 – 15.0 – 20.0 ns tgoeen B 16 Global OE Output Enable – 7.0 – 9.0 – 10.5 ns tgoedis C 17 Global OE Output Disable – 7.0 – 9.0 – 10.5 ns twh – 18 Ext. Sync. Clk. Pulse Duration, High 3.0 – 4.0 – 5.0 – ns twl – 19 Ext. Sync. Clk. Pulse Duration, Low 3.0 – 4.0 – 5.0 – ns tsu3 – 20 I/O Reg. Setup Time before Ext. Sync. Clk. (Y2, Y3) 3.0 – 3.5 – 4.5 – ns th3 – 21 I/O Reg. Hold Time after Ext. Sync. Clk. (Y2, Y3) 0.0 – 0.0 – 0.0 – ns 1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions Section. Table 2-0030-16/125,100, 80 5 1996 ISP Encyclopedia 5 Page Specifications ispLSI and pLSI 1016E ispLSI 1016E Shift Register Layout Data In (SDI) D A T A 79... 159... High Order Shift Register Low Order Shift Register D A T A ...0 ...80 SDO SDI 10... 9 E2CMOS Cell Array 0182B-16 ... 0 SDO Note: A logic “1” in the Address Shift Register bit position enables the row for programming or verification. A logic “0” disables it. 11 1996 ISP Encyclopedia 11 Page

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Número de pieza	Descripción	Fabricantes
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