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PDF PI90LVB048A Data sheet ( Hoja de datos )

Número de pieza PI90LVB048A
Descripción LVDS Quad Flow-Through Differential Line Receivers
Fabricantes Pericom Semiconductor 
Logotipo Pericom Semiconductor Logotipo



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No Preview Available ! PI90LVB048A Hoja de datos, Descripción, Manual

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PI90LV048A/PI90LVT048A
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3V LVDS Quad Flow-Through
Differential Line Receivers
Features
• 500 Mbps (250 MHz) switching rates
• Flow-through pinout simplifies PCB layout
• 150ps channel-to-channel skew (typical)
• 100ps differential skew (typical)
• 2.7ns maximum propagation delay
• 3.3V power supply design
• High impedance LVDS inputs on power down
• Low Power design (40mW, 3.3V static)
• Wide common-mode input voltage range: 0.2V to 2.7V
• Accepts small swing (350mV typical) differential signal levels
• Supports open, short and terminated input fail-safe
• Low-power state when in fail-safe
• Conforms to ANSI/TIA/EIA-644 Standard
• Industrial temperature operating range (–40°C to +85°C)
• Packaging (Pb-free & Green available):
- 16-pin SOIC (W)
- 16-pin TSSOP (L)
Block Diagram
RIN1+
4 Places
PI90LVT048A
100
Only
RIN1–
R1
ROUT1
RIN2+
RIN2–
R2
ROUT2
RIN3+
RIN3–
R3
ROUT3
RIN4+
RIN4–
R4
ROUT4
EN
EN
Description
ThePI90LV048A/PI90LVT048Aquad flow-throughdifferentialline
receivers are designed for applications requiring ultra low-power
dissipation and high data rates. The device is designed to support
data rates in excess of 500 Mbps (250 MHz) using Low Voltage
Differential Signaling (LVDS) technology.
The devices accept low-voltage (350 mV typical) differential input
signals and translates them to 3V CMOS output levels. The receiver
supports a 3-state function, which may be used to multiplex outputs,
and also supports open, shorted and terminated (100-ohms) input fail-
safe. The receiver output will be HIGH for all fail-safe conditions.
PI90LVT048A features integrated parallel termination resistors
(nominally 110-ohms) that eliminate the requirement for four dis-
crete termination resistors and reduce stud length. PI90LV048A
inputs are high impedance and require an external termination
resistor when used in a point-to-point connection. The devices
have a flow-through pinout for easy PCB layout.
The EN and EN inputs are ANDed together and control the 3-state
outputs. The enables are common to all four receivers. The
PI90LV048A and companion LVDS line driver (eg. PI90LV047A)
provide a new alternative to high-power PECL/ECL devices for
high-speed point-to-point interface applications.
Pin Configuration
RIN1–
RIN1+
RIN2+
RIN2–
RIN3–
RIN3+
RIN4+
RIN4–
1
2
3
4
5
6
7
8
16 EN
15 ROUT1
14 ROUT2
13 VCC
12 GND
11 ROUT3
10 ROUT4
9 EN
Truth Table
EN
Enables
EN
H L or Open
All other combinations of ENABLE inputs
Inputs
RIN+ – RIN–
VID 0.1V
VID –0.1V
Full fail-safe OPEN/SHORT or terminated
X
Outputs
ROUT
H
L
H
Z
1
PS8608A
10/04/04

1 page




PI90LVB048A pdf
PI90LV048A/PI90LVT048A
3V LVDS Quad Flow-Through
1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788D9900i11f22f33e4455r66e77n8899t00i11a2233l44L5566i77n8899e0011R2211e2233c44e55i66v7788e99r0011s22
Parameter Measurement Information(continued)
EN When EN = GND or OPEN
1.5V
1.5V
EN When EN = VCC
1.5V
Output When VID = –100mV
tPHZ
Output When VID = +100mV
tPLZ
0.5V
0.5V
1.5V
tPZL
50%
tPZH
50%
Typical Application
Figure 4. Receiver 3-State Delay Waveforms
Enable
Data Input
1/4 PI90LV047A
1/4 PI90LV048A
RT 100
+
Data
Output
Figure 5. Point-to-Point Application
3V
0V
3V
0V
VCC
VOL
VOH
GND
5
PS8608A
10/04/04

5 Page










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