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PDF FS8160 Data sheet ( Hoja de datos )
| Número de pieza | FS8160 | |
| Descripción | Dual Phase-locked Loop IC | |
| Fabricantes | Himark | |
| Logotipo |  |
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FS8160 1.1 GHz/1.1 GHz Dual Phase-locked Loop IC
HiMARK Technology, Inc. reserves the right to change the product described in this datasheet. All information con-
tained in this datasheet is subject to change without prior notice. HiMARK Technology, Inc. assumes no responsibility
for the use of any circuits shown in this datasheet.
Description
The FS8160 is a serial data input, fully programmable dual phase-locked loop IC for use
in the local oscillator subsystem of radio transceivers. When combined with external
VCOs, the FS8160 becomes the core of a very low power dual frequency synthesizer well-
suited for mobile communication applications. The FS8160 is pin-compatible with
National Semiconductor’s LMX1602 IC.
Features
Supply voltage operating range: 2.7 to 3.6 V
Maximum input frequency: 1.1 GHz/1.1 GHz (main/auxiliary)
Low current consumption (IDD,total typically 5 mA at VDD,main = VDD,aux = 3.0 V and < 1
µA in power down mode)
16-bit programmable input (both main and auxiliary) frequency dividers (including a
÷ 16/17 prescaler) with divide ratio range from 240 to 65535
12-bit programmable reference (both main and auxiliary) frequency dividers with
divide ratio range from 2 to 4095
Programmable charge pump output
Digital-filtered lock detect output
16 pin, plastic TSSOP (0.65 mm pitch)
Package and Pin Assignment
16 pin, plastic TSSOP (dimensions in mm)
FOLD 1
XIN 2
XOUT 3
VSSA 4
FINA 5
VDDA 6
DOA 7
ENA 8
16 CLK
15 DATA
14 LE
13 VSSM
12 FINM
11 VDDM
10 DOM
9 ENM
Page 1
April 2003
1 page  
FS8160
Electrical Characteristics (continued)
(VDD,main = VDD,aux = VDD = 3.0 V, TA = 25 °C unless otherwise noted)
Parameter
CLK to LE setup time
CLK pulse width logic HIGH
CLK pulse width logic LOW
LE pulse width
CHARGE PUMP
Charge pump output current
Charge pump high-Z state current
Symbol
tSU2
tPWH
tPWL
tPW
Condition
min.
50
50
50
50
IDO,source
IDO,sink
IDO,high-Z
High gain mode,
VDOM,VDOA = VDD/2
Low gain mode,
VDOM,VDOA = VDD/2
High gain mode,
VDOM,VDOA = VDD/2
Low gain mode,
VDOM,VDOA = VDD/2
0.5 V ≤ VDOM,VDOA ≤ VDD – 0.5 V
Value
typ. max.
–1600
–160
+1600
+160
1
Unit
nS
nS
nS
nS
µA
µA
µA
µA
nA
Page 5
April 2003
5 Page 
FS8160
Lock Detector
The lock detector incorporates a filter which compares the phase error between the inputs
to the PFD to an R-C generated delay of 15 ns. To enter the locked state (output is high),
the phase error must be less than 15 ns for four (4) consecutive cycles. Once in the locked
state, the generated R-C delay is changed to 30 ns. To exit the locked state (i.e. lock detec-
tor output goes low), the phase error must become greater than the 30 ns delay. When the
PLL is in stand-by mode, the lock detector output is forced low. A flow chart representing
the operation of the lock detector is given below.
Start
Phase error
< 15 ns
Yes
Phase error
< 15 ns
Yes
Phase error
< 15 ns
Yes
Phase error
< 15 ns
Un-locked state
(output LOW)
No
No
No
No
Yes
Locked state
(output HIGH)
No
Phase error
> 30 ns
Yes
Crystal Oscillator
The internal crystal oscillator circuitry may be used in either of two modes: crystal mode
— with an external crystal resonator (crystal mode) or logic mode — with an external ref-
erence frequency source such as a TCXO (logic mode). The FOLD[3:0] control bits select
Page 11
April 2003
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet FS8160.PDF ] | |
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