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PDF CRD5381 Data sheet ( Hoja de datos )
| Número de pieza | CRD5381 | |
| Descripción | Audio A/D Converter w/ Asynchronous Decimation Filter Reference Design | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CRD5381
Audio A/D Converter w/ Asynchronous Decimation Filter
Reference Design
Features
Analog Performance
Advanced Multi-bit Delta-sigma Architecture
24-bit Conversion
120 dB Dynamic Range
-110 dB THD+N
Performance insensitivity to Input Clock Jitter
Digital Filter Characteristics
125 dB Stop-band Rejection
Phase-Matched Outputs
System Features
Output Sample Rate Determined by Input
Word, Left/Right, or Fsync Clock
No External Master Clock Required
Easily Scalable for Additional Channels
Sample Rates from 27 kHz to 192 kHz
Four-Channel Time-Division Multiplexed
Output
Two Independent Stereo, Left-Justified
Outputs
LEFT
RIGHT
CS5381 A
Quad Speed SDOUT
Slave Mode
CS8421 A
SDIN Master Input SDOUT
Slave Ouput
22
Differential Analog
Inputs 1-4
22
LEFT
RIGHT
CS5381 B
Quad Speed SDOUT
Slave Mode
TDM ENABLE
SDOUT A
TDM/SDOUT B
PCM Data Ouput/
Serial Clock Input
Header, J4
LRCK INPUT SCLK INPUT
TDM IN
CS8421 B
SDIN Master Input SDOUT
Slave Output
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
MAY ‘05
DS563RD1
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1.2 CS8421 Output and the Interface Clock Domain
CRD5381
1.2.1 CS8421 Output System Clocking
The CS8421 serial output is configured as a system clock slave. The advantages are:
• Output sample rate is dependent on the frequency of the incoming word clock (OLRCK), set by the user.
• Outputs of multiple CS8421 devices are synchronous.
• Multiple devices can be configured in a Time Division Multiplexed (TDM) multi-channel interface format.
As mentioned in “CS8421 Input Operational Mode” on page 4, the input of the CS8421 is configured as a
master, with the master clock frequency = 128*Fsi (or ILRCK). To accommodate this serial input mode, and
to set the serial output to slave, the MS_SEL pin is connected to +3.3 V.
1.2.2 Serial Audio Output Port Options and Selection of Data Resolution and Dither
The CS8421 provides multiple options for the serial audio output port. These options include:
• Output Data Format of Left-Justified, Right-Justified, I²S or TDM
• Audio output data resolution of the SRC can be set to 16, 20, 24, or 32-bits. Dithering is applied and is
automatically scaled to the selected output word length. This dither is not correlated between left and
right channels.
Output word-length and serial data format are selected with either a pull-up or pull down resistor connected
to the SAOF pin of the CS8421. Please refer to Table 3 in the CS8421 data sheet for details [3].
The serial audio output of the CRD5381 is configured to operate in either dual 24-bit Left-Justified formats
or a 4-channel 24-bit TDM output.
1.2.3 Clocking
In order to ensure proper operation of the CS8421, the clock or crystal attached to XTI must simultaneously
satisfy the requirements of LRCK for both the input and output as follows:
• If the input is set to master, Fsi ≤ XTI/128 and Fso ≤ XTI/130.
• If the output is set to master, Fso ≤ XTI/128 and Fsi ≤ XTI/130.
• If both input and output are set to slave, XTI ≥ 130*[maximum(Fsi,Fso)], XTI/Fsi < 3750, and XTI/Fso <
3750.
In the example application in this data sheet, the input serial port is set to master, and generates serial
clocks for a sampling rate of XTI/128. The output serial port is set as slave, and can receive a left-right clock
that is ≤ XTI/130. The serial bit-clock frequency is always 64*left-right clock.
1.2.4 SRC Locking and Varispeed
The SRC calculates the ratio between the input sample rate and the output sample rate, and uses this in-
formation to set up various parameters inside the SRC block. The SRC takes approximately 4200/Fso
(8.75 ms at Fso of 48 kHz) to make this calculation.
The SRC_UNLOCK pin is used to indicate when the SRC is not locked. When RST is asserted, or if there
is a change in Fsi or Fso, SRC_UNLOCK will be set high. The SRC_UNLOCK pin will continue to be high
until the SRC has reacquired lock and settled, at which point it will transition low. When the SRC_UNLOCK
pin is set low, SDOUT is outputting valid audio data. This can be used to signal a DAC to un-mute its output.
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CRD5381
RESET
J16
Signal Ground
OVERFLOW A
OVERFLOW B
SRC UNLOCK A
SRC UNLOCK B
Figure 7. Status Indicator and Reset Header, J16
2.6 Analog Inputs
The CRD5381 provides four fully differential analog inputs via J9, J11, J7, and J12; shown in Figure 9 and
Figure 10. Each analog input has the required analog circuitry to optimize the performance of each CS5381.
The input buffer to each CS5381 device has unity gain, and the CRD5381 differential input amplitude re-
quired to generate a full-scale digital output is typically 5.65 Vpp.
If extra analog input circuitry is required in the user’s design, it should drive a buffer equivalent to the con-
tents of the dotted boxes shown in Figure 9 and in Figure 10 labeled “CS5381 Required Input Circuitry”. In
this case, all components outside the dotted boxes in Figure 9 and Figure 10 should be removed from the
design.
2.7 Power
The CRD5381 requires the user to supply +3.3 V (J6) and ±12 V (J2 and J1) to the board. Onboard regula-
tors supply the required +5 V and +2.5 V. All voltage inputs must be referenced to the single black banana-
type ground connector (J5). Zener Diodes Z1 and Z2 (shown in Figure 14) are used to protect the CRD5381
circuitry from accidental connection of a reversed polarity supply or a supply of over ± 13 V to J1 and J2.
WARNING: Please refer to the CS5381 and CS8421 data sheet for allowable voltage levels.
2.8 Grounding and Power Supply Decoupling
The CS5381 and CS8421 require careful attention to power supply and grounding arrangements in order
to optimize performance. Figure 8 provides an overview of the connections on the CRD5381; Figure 15
shows the component placement. Figure 16 shows the top layout, Figure 17 shows the bottom layout, Fig-
ure 18 shows the power plane, and Figure 19 shows the ground plane. The decoupling capacitors are lo-
cated as close to the CS5381 and CS8421 as possible. Extensive use of ground plane fill in the evaluation
board yields large reductions in radiated noise.
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11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet CRD5381.PDF ] | |
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