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PDF CRD44130-FB Data sheet ( Hoja de datos )
| Número de pieza | CRD44130-FB | |
| Descripción | 20 W x 2 + 40 W x 1 PWM Amplifier Reference Design | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CRD44130-FB
20 W x 2 + 40 W x 1 PWM Amplifier Reference Design
Features
Two Full-Bridge Channels, 20 W each
(@ 10% THD+N)
One Parallel Full-Bridge Channel, 40 W
(@ 10% THD+N)
< 0.3% THD+N at 12 W
Thermally Enhanced QFN Package Requires
No Heat Sink
Accepts Analog Audio or S/PDIF Digital Audio
Inputs
Onboard FPGA Converts Stereo Inputs to
Properly Filtered 2.1 Outputs
CS44600 Spread Spectrum Modulation
Reduces EMI Emissions
Thermal, Over-Current, and Under-Voltage
Protection
> 85% Amplifier Efficiency
Can be operated as a Stand-Alone Board
through On-Board Controls or with Windows®
Compatible Graphical User Interface
Demonstrates Recommended Layout and
Grounding Arrangements
120 W Switch Mode Power Supply
(SMPS)
+5.0 V
+18 V
+18 V
Channel 1 (L)
Channel 2 (R)
CS44130
(Power
Stage)
LPF
LPF
8Ω
8Ω
Audio
Inputs and
Control
Logic
PCM Clocks
& Data
FPGA for
Stereo to
2.1
Conversion
PCM Clocks
& Data
CS44600
(PWM
Controller)
I2C Host Control
+18 V
Channel 3 (LFE)
CS44130
(Power
Stage)
LPF
4Ω
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
AUGUST '06
DS690RD2
1 page  
CRD44130-FB
1. SYSTEM OVERVIEW
The CRD44130-FB reference design is an excellent means for evaluating the CS44130 dual full-bridge power stage.
This design includes analog and digital input capability, an FPGA for stereo to 2.1 conversion, a digital Class-D
PWM modulator, one stereo full-bridge power stage, and one parallel full-bridge power stage- all on a two-layer
board.
The CRD44130-FB schematic set is shown in Figures 5 through 10 and the board layout is shown in Figures 11
through 13.
1.1 CS44600 PWM Modulator
A complete description of the CS44600 is included in the CS44600 product data sheet, located at
http://www.cirrus.com.
The CS44600 converts linear PCM data to pulse width modulated (PWM) output. It uses a crystal-based
sample rate converter (SRC) to eliminate serial audio interface jitter and maintain a constant PWM switching
rate of 384 kHz, resulting in high-quality sound output.
PCM data and clocks are input from either the CS8416 (S/PDIF Receiver) or CS5341 (Stereo ADC).
1.2 CS44130 Power Stage
A complete description of the CS44130 is included in the CS44130 product data sheet, located at
http://www.cirrus.com.
The CS44130 is a high-voltage PWM amplifier power stage. It integrates four half-bridge drivers and fault
protection. For the CRD44130-FB, one of the CS44130 parts is configured with full-bridge outputs and one
is configured with a single parallel full-bridge output. Care should be taken to not connect the black speaker
connectors to ground as these outputs are driven.
1.3 Stereo to 2.1 Conversion
The CRD44130-FB includes an FPGA programmed to convert stereo PCM audio data to 2.1 audio. The 2.1
conversion capability is enabled and disabled by pressing push-button S1, and is indicated by LED D14.
When 2.1 is enabled, the J1 speaker outputs will produce midrange and high-frequency audio content for
left and right channels. The J2 speaker output will produce low-frequency mono content with a crossover
frequency of 120 Hz for use with a subwoofer. Figure 14 on page 28 shows the system frequency response
with 2.1 enabled.
When 2.1 is disabled, the J1 speaker outputs will produce full-range audio content for left and right chan-
nels, and the J2 speaker output will produce full-range audio content for the left channel only. Figure 15 on
page 29 and Figure 16 on page 30 show the system frequency response with 2.1 disabled.
1.4 CS8416 Digital Audio Receiver
The operation of the CS8416 receiver and a discussion of the digital audio interface are described in the
CS8416 data sheet, located at http://www.cirrus.com.
The CS8416 converts the S/PDIF data stream into PCM data, which is then supplied to the CS44600. The
CS8416 operates in master mode with RMCK = 256*Fs. The digital interface format is set to Left-Justified
(24-bit).
D17 (RERR) indicates a S/PDIF receiver error, such as loss of lock or a non-PCM data input.
DS690RD2
5
5 Page 
2.4 Board Connections
CRD44130-FB
2.4.1
Audio Inputs
The CRD44130-FB provides stereo analog and digital inputs. The Analog inputs are J9 (left input) and
J10 (right input). When analog inputs are used, full scale output is achieved when the analog input level
is 2.0 Vrms. S/PDIF digital input can be either the optical receiver J8 or the RCA connector J11. When a
valid PCM S/PDIF digital audio signal is present on J8 or J11 (cannot be present on both simultaneously),
the CRD44130-FB outputs the program material present on that digital input. When a valid PCM S/PDIF
digital audio signal is not present on either J8 or J11 (or both are mistakenly driven simultaneously), the
CRD44130-FB outputs the program material present on its analog inputs. Due to the timing constraints of
the FPGA, digital audio inputs must be limited to a sample rates of 32-96 kHz.
2.4.2
Speaker Outputs
The CRD44130-FB provides speaker-level left, right, and low-frequency speaker outputs. Left and right
channel output connections are made through speaker terminal J1; and the low-frequency speaker output
connection is made through speaker terminal J2. Refer to Figure 4 for speaker connection details.
J1
J2
LFE-
LFE+
R+ L+
R- L-
Figure 4. Speaker Output Connections
When LED D14 is lit, this indicates that 2.1 is enabled. This means that the left, right, and low-frequency
channels will be filtered according to the frequency response shown in Figure 14. In this mode, the low-
frequency channel will be the filtered sum of the left and right channels. When 2.1 is disabled (by pressing
push-button S1), the board provides no filtering and the low-frequency output produces full bandwidth left-
channel audio.
DS690RD2
11
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| PDF Descargar | [ Datasheet CRD44130-FB.PDF ] | |
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