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PDF AD9942 Data sheet ( Hoja de datos )
| Número de pieza | AD9942 | |
| Descripción | 14-Bit CCD Signal Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Dual-Channel, 14-Bit CCD Signal Processor
with Precision Timing™ Core
AD9942
FEATURES
40 MHz correlated double sampler (CDS)
0 dB to 18 dB, 9-bit variable gain amplifier (VGA)
40 MSPS analog-to-digital converter (ADC)
Optical black clamp (CLPOB) with variable level control
Complete on-chip timing driver
Precision Timing core with <550 ps resolution
On-chip 3 V horizontal and RG drivers
4-phase H-clock mode
100-lead, 9 mm × 9 mm, CSP_BGA package
APPLICATIONS
Signal processor for dual-channel CCD outputs
Digital still cameras
Digital video cameras
High speed digital imaging applications
GENERAL DESCRIPTION
The AD9942 is a highly integrated dual-channel CCD signal
processor for digital still camera applications. Each channel is
specified at pixel rates of up to 40 MHz. The AD9942 consists of
a complete analog front end with analog-to-digital conversion,
combined with a programmable timing driver. The Precision
Timing core allows high speed clocks to be adjusted with
550 ps resolution.
The analog front end uses black level clamping and includes a
VGA, a 40 MSPS ADC, and a CDS. The timing driver provides
the high speed CCD clock drivers for RG_A and RG_B, as well
as the H1A to H4A and H1B to H4B outputs. The 6-wire serial
interface is used to program the AD9942.
Available in a space-saving, 9 mm × 9 mm, CSP_BGA package,
the AD9942 is specified over an operating temperature range of
−25°C to +85°C.
CCDIN_A
CCDIN_B
FUNCTIONAL BLOCK DIAGRAM
REFT_A REFB_A
REFT_B REFB_B
AD9942
VREF_A
VREF_B
CDS
CDS
VGA
0dB ~ 18dB
0dB ~ 18dB
VGA
ADC
CLAMP
CLAMP
ADC
14
DOUT_A
14
DOUT_B
RG_A
RG_B
H1A TO H4A
H1B TO H4B
4 HORIZONTAL
DRIVERS
4
INTERNAL CLOCKS
PRECISION
TIMING
CORE
SYNC
GENERATOR
INTERNAL
REGISTERS
CLI_A
CLI_B
SCK_A
SCK_B
HD_A VD_A HD_B VD_B
Figure 1.
SL_A SDATA_A SL_B SDATA_B
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
AD9942
ANALOG SPECIFICATIONS
TMIN to TMAX, AVDD_X = DVDD_X = 3.0 V, fCLI = 40 MHz, typical timing specifications, unless otherwise noted. X = A, B.
Table 3.
Parameter
CDS
Gain
Allowable CCD Reset Transient1
Max Input Range Before Saturation
Max CCD Black Pixel Amplitude
Min
1.0
VARIABLE GAIN AMPLIFIER (VGA_X)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
Min Gain (Code 0)
Max Gain (Code 511)
CLPOB
Clamp Level Resolution
Clamp Level
Min Clamp Level
Max Clamp Level
CHN_A AND CHN_B ADC
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
VOLTAGE REFERENCE
Reference Top Voltage (REFT_X)
Reference Bottom Voltage (REFB_X)
SYSTEM PERFORMANCE
VGA Gain Accuracy
Min Gain (Code 0)
Max Gain (Code 511)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
1.0
2.0
−1.0
−0.5
17.5
Typ
Max Unit
Notes
0
500
±100
dB
mV
V p-p
mV
Measured at 12 dB VGA gain
(Typ = 70 mV at 15 dB and 50 mV at 18 dB)
512
Guaranteed
V p-p
V p-p
Steps
0 dB
18 dB
256
0
1023
Steps
LSB
LSB
4 LSB/step
Measured at ADC output
± 0.5
+1.0 LSB
Guaranteed
2.0 V
2.0 V
1.0 V
Specifications include entire signal chain
0 +0.5 dB
18 18.5 dB
0.15 % 12 dB gain applied
3 LSB rms AC grounded input, 6 dB gain applied
50 dB Measured with step change on supply
1 Input signal characteristics defined as follows:
500mV TYP
RESET TRANSIENT
100mV MAX
OPTICAL BLACK PIXEL
1V MAX
INPUT SIGNAL RANGE
Rev. A | Page 5 of 36
5 Page 
TERMINOLOGY
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Therefore,
every code must have a finite width. No missing codes
guaranteed to 12-bit resolution indicates that all 4096 codes
must be present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9942 from a true straight
line. The point used as zero scale occurs 0.5 LSB before the first
code transition. Positive full scale is defined as a level 1 LSB
and 0.5 LSB beyond the last code transition. The deviation is
measured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage
of the 2 V ADC full-scale signal. The input signal is always
appropriately gained up to fill the ADC’s full-scale range.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship
1 LSB = (ADC full scale/2n codes)
where n is the bit resolution of the ADC. For the AD9942,
1 LSB is approximately 122.0 μV.
AD9942
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.
Matching Error
The matching error refers to the Channel A to Channel B
mismatch after post-ADC correction calibration has been
applied to remove gain error between Channel A and
Channel B.
Crosstalk
The crosstalk is measured while applying a full-scale step to
one channel and measuring the interference on the opposite
channel.
Crosstalk
(dB) =
20
×
log
⎜⎜⎝⎛
Interference
16,384
(LSB)
⎟⎟⎠⎞
Rev. A | Page 11 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9942.PDF ] | |
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