PDF SM560 Data sheet ( Hoja de datos )

Número de pieza	SM560
Descripción	Spread Spectrum Clock Generator
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com Features • 25- to 108-MHz operating frequency range • Wide (9) range of spread selections • Accepts clock and crystal inputs • Low power dissipation • 3.3V = 85 mw (50 MHz) • Frequency Spread disable function • Center Spread modulation • Low cycle-to cycle jitter • Eight-pin SOIC package SM560 Spread Spectrum Clock Generator Applications • VGA controllers • LCD panels and monitors • Printers and multi-function devices (MFP) Benefits • Peak electromagnetic interference (EMI) reduction by 8 to 16 dB • Fast time to market • Cost reduction Block Diagram 250 K Xin/ CLK 1 4 pf Xout 8 VDD 2 VSS 3 8 pF REFERENCE DIVIDER MODULATION CONTROL INPUT DECODER LOGIC 5 SSCC 67 S1 S0 Pin Configuration PD CP FEEDBACK DIVIDER LF VCO Xin/CLK VDD VSS SSCLK 1 2 3 4 DIVIDER AND MUX 4 SSCLK 8 Xout 7 S0 6 S1 5 SSCC Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-07020 Rev. E Revised June 25, 2004 1 page SM560 Clock Frequency = fc = 65MHz Clock Period = Tc =1/65 MHz = 15.4 ns 50 % 50 % Tc = 15.4 ns If this clock is applied to the Xin/CLK pin of the SM560, the output clock at pin 4 (SSCLK) will be sweeping back and forth between two frequencies. These two frequencies, F1 and F2, are used to calculate to total amount of spread or bandwidth applied to the reference clock at pin 1. As the clock is making the transition from f1 to f2, the amount of time and sweep waveform play a very important role in the amount of EMI reduction realized from an SSCG clock. The modulation domain analyzer is used to visualize the sweep waveform and sweep period. The left side of Figure 2 shows the modulation profile of a 65-MHz SSCG clock. Notice that the actual sweep waveform is not a simple sine or sawtooth waveform. The right side of Figure 2 is a scan of the same SSCG clock using a spectrum analyzer. In this scan you can see a 6.48-dB reduction in the peak RF energy when using the SSCG clock. Modulation Rate Spectrum Spread Clock Generators utilize frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (Fmax) and minimum frequency of the clock (Fmin) determine this band of frequencies. The time required to transition from Fmin to Fmax and back to Fmin is the period of the Modulation Rate, Tmr. Modulation Rates of SSCG clocks are generally referred to in terms of frequency or Fmod = 1/Tmod. The input clock frequency, Fin, and the internal divider count, Cdiv, determine the Modulation Rate. In some SSCG clock generators, the selected range determines the internal divider count. In other SSCG clocks, the internal divider count is fixed over the operating range of the part. The SM560 and SM561 have a fixed divider count, as listed below. Device Cdiv SM560 SM561 1166 2332 (All Ranges) (All Ranges) Example: Device = Fin = Range = SM560 65 MHz S1 = 1, S0 = M Then; Modulation Rate = Fmod = 65 MHz/1166 = 55.8 kHz. SMpoedBcutWrlua=tmio2An.4nP6ar%loyfzileer -6.58 dB Figure 2. SSCG Clock, SM560, Fin = 65 MHz Document #: 38-07020 Rev. E Page 5 of 8 5 Page

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