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PDF LPC2378 Data sheet ( Hoja de datos )
| Número de pieza | LPC2378 | |
| Descripción | Single-chip 16-bit/32-bit microcontrollers | |
| Fabricantes | NXP Semiconductors | |
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LPC2378
Single-chip 16-bit/32-bit microcontrollers; 512 kB flash with
ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
Rev. 01 — 6 December 2006
Preliminary data sheet
1. General description
The LPC2378 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU with
real-time emulation that combines the microcontroller with 512 kB of embedded
high-speed flash memory. A 128-bit wide memory interface and a unique accelerator
architecture enable 32-bit code execution at the maximum clock rate. For critical
performance in interrupt service routines and DSP algorithms, this increases performance
up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit
Thumb mode reduces code by more than 30 % with minimal performance penalty.
The LPC2378 is ideal for multi-purpose serial communication applications. It incorporates
a 10/100 Ethernet Media Access Controller (MAC), USB full speed device with 4 kB of
endpoint RAM, four UARTs, two CAN channels, an SPI interface, two Synchronous Serial
Ports (SSP), three I2C interfaces, an I2S interface, and an External Memory Controller
(EMC). This blend of serial communications interfaces combined with an on-chip 4 MHz
internal oscillator, SRAM of 32 kB, 16 kB SRAM for Ethernet, 8 kB SRAM for USB and
general purpose use, together with 2 kB battery powered SRAM make this device very
well suited for communication gateways and protocol converters. Various 32-bit timers, an
improved 10-bit ADC, 10-bit DAC, PWM unit, a CAN control unit, and up to 104 fast GPIO
lines with up to 50 edge and up to four level sensitive external interrupt pins make these
microcontrollers particularly suitable for industrial control and medical systems.
2. Features
I ARM7TDMI-S processor, running at up to 72 MHz.
I Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Flash program memory is on the ARM
local bus for high performance CPU access.
I 32 kB of SRAM on the ARM local bus for high performance CPU access.
I 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
I 8 kB SRAM for general purpose DMA use also accessible by the USB.
I Dual Advanced High-performance Bus (AHB) system that provides for simultaneous
Ethernet DMA, USB DMA, and program execution from on-chip flash with no
contention between those functions. A bus bridge allows the Ethernet DMA to access
the other AHB subsystem.
I EMC provides support for static devices such as flash and SRAM as well as off-chip
memory mapped peripherals.
I Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
I General Purpose AHB DMA controller (GPDMA) that can be used with the SSP serial
interfaces, the I2S port, and the Secure Digital/MultiMediaCard (SD/MMC) card port,
as well as for memory-to-memory transfers.
1 page  
NXP Semiconductors
6. Pinning information
6.1 Pinning
LPC2378
Fast communication chip
1 108
LPC2378FBD144
36 73
Fig 2. LPC2378 pinning
002aac584
6.2 Pin description
Table 3. Pin description
Symbol
Pin
P0[0] to P0[31]
P0[0]/RD1/TXD/
SDA1
66[1]
P0[1]/TD1/RXD3/ 67[1]
SCL1
P0[2]/TXD0
P0[3]/RXD0
P0[4]/
I2SRX_CLK/
RD2/CAP2[0]
141[1]
142[1]
116[1]
Type
I/O
I/O
I
O
I/O
I/O
O
I
I/O
I/O
O
I/O
I
I/O
I/O
I
I
Description
Port 0: Port 0 is a 32 bit I/O port with individual direction controls for each bit. The
operation of port 0 pins depends upon the pin function selected via the Pin Connect
block.
P0[0] — General purpose digital input/output pin.
RD1 — CAN1 receiver input.
TXD3 — Transmitter output for UART3.
SDA1 — I2C1 data input/output (this is not an open drain pin).
P0[1] — General purpose digital input/output pin.
TD1 — CAN1 transmitter output.
RXD3 — Receiver input for UART3.
SCL1 — I2C1 clock input/output (this is not an open drain pin).
P0[2] — General purpose digital input/output pin.
TXD0 — Transmitter output for UART0.
P0[3] — General purpose digital input/output pin.
RXD0 — Receiver input for UART0.
P0[4] — General purpose digital input/output pin.
I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave.
Corresponds to the signal SCK in the I2S-bus specification.
RD2 — CAN2 receiver input.
CAP2[0] — Capture input for Timer 2, channel 0.
LPC2378_1
Preliminary data sheet
Rev. 01 — 6 December 2006
© NXP B.V. 2006. All rights reserved.
5 of 54
5 Page 
NXP Semiconductors
LPC2378
Fast communication chip
Table 3. Pin description …continued
Symbol
Pin Type Description
P2[7]/RD2/
RTS1/
TRACEPKT2
95[1]
I/O P2[7] — General purpose digital input/output pin.
I RD2 — CAN2 receiver input.
O RTS1 — Request to Send output for UART1.
O TRACEPKT2 — Trace Packet, bit 2.
P2[8]/TD2/
TXD2/
TRACEPKT3
93[1]
I/O P2[8] — General purpose digital input/output pin.
O TD2 — CAN2 transmitter output.
O TXD2 — Transmitter output for UART2.
O TRACEPKT3 — Trace Packet, bit 3.
P2[9]/
USB_CONNECT1/
RXD2/
EXTIN0
92[1]
I/O P2[9] — General purpose digital input/output pin.
O USB_CONNECT1 — USB1 Soft Connect control. Signal used to switch an external
1.5 kΩ resistor under the software control. Used with the SoftConnect USB feature.
I RXD2 — Receiver input for UART2.
I EXTIN0 — External Trigger Input.
P2[10]/EINT0
76[6]
I/O P2[10] — General purpose digital input/output pin.
Note: LOW on this pin while RESET is LOW forces on-chip boot-loader to take over
control of the part after a reset.
I EINT0 — External interrupt 0 input.
P2[11]/EINT1/
MCIDAT1/
I2STX_CLK
75[6]
I/O P2[11] — General purpose digital input/output pin.
I EINT1 — External interrupt 1 input.
O MCIDAT1 — Data line for SD/MMC interface.
I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave.
Corresponds to the signal SCK in the I2S-bus specification.
P2[12]/EINT2/
MCIDAT2/
I2STX_WS
73[6]
I/O P2[12] — General purpose digital input/output pin.
I EINT2 — External interrupt 2 input.
O MCIDAT2 — Data line for SD/MMC interface.
I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the
slave. Corresponds to the signal WS in the I2S-bus specification.
P2[13]/EINT3/
MCIDAT3/
I2STX_SDA
71[6]
I/O P2[13] — General purpose digital input/output pin.
I EINT3 — External interrupt 3 input.
O MCIDAT3 — Data line for SD/MMC interface.
I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver.
Corresponds to the signal SD in the I2S-bus specification.
P3[0] to P3[31]
I/O Port 3: Port 3 is a 32 bit I/O port with individual direction controls for each bit. The
operation of port 3 pins depends upon the pin function selected via the Pin Connect
block. Pins 8 through 22, and 27 through 31 of this port are not available.
P3[0]/D0
137[1] I/O P3[0] — General purpose digital input/output pin.
I/O D0 — External memory data line 0.
P3[1]/D1
140[1] I/O P3[1] — General purpose digital input/output pin.
I/O D1 — External memory data line 1.
P3[2]/D2
144[1] I/O P3[2] — General purpose digital input/output pin.
I/O D2 — External memory data line 2.
P3[3]/D3
2[1] I/O P3[3] — General purpose digital input/output pin.
I/O D3 — External memory data line 3.
LPC2378_1
Preliminary data sheet
Rev. 01 — 6 December 2006
© NXP B.V. 2006. All rights reserved.
11 of 54
11 Page | ||
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| PDF Descargar | [ Datasheet LPC2378.PDF ] | |
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