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PDF FS6128-01 Data sheet ( Hoja de datos )
| Número de pieza | FS6128-01 | |
| Descripción | PLL Clock Generator IC | |
| Fabricantes | AMI | |
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AMERICAN MICROSYSTEMS, INC.
FS6128-01
PLL Clock Generator IC with VCXO
April 2000
1.0 Features
• Phase-locked loop (PLL) device synthesizes output
clock frequency from crystal oscillator or external ref-
erence clock
• On-chip tunable voltage-controlled crystal oscillator
(VCXO) allows precise system frequency tuning
• Typically used for generation of MPEG-2 decoder
clock
• 3.3V supply voltage
• Small circuit board footprint (8-pin 0.150″ SOIC)
• Custom frequency selections available - contact your
local AMI Sales Representative for more information
Figure 1: Pin Configuration
2.0 Description
The FS6128 is a monolithic CMOS clock generator IC
designed to minimize cost and component count in digital
video/audio systems.
At the core of the FS6128 is circuitry that implements a
voltage-controlled crystal oscillator when an external
resonator (nominally 13.5MHz) is attached. The VCXO
allows device frequencies to be precisely adjusted for use
in systems that have frequency matching requirements,
such as digital satellite receivers.
A high-resolution phase-locked loop generates an output
clock (CLK) through a post-divider. The CLK frequency is
ratiometrically derived from the VCXO frequency. The
locking of the CLK frequency to other system reference
frequencies can eliminate unpredictable artifacts in video
systems and reduce electromagnetic interference (EMI)
due to frequency harmonic stacking.
XIN 1
VDD 2
XTUNE 3
VSS 4
8 XOUT
7 VSS
6 n/c
5 CLK
Table 1: Crystal / Output Frequencies
DEVICE
fXIN (MHz)
CLK (MHz)
FS6128-01
13.5
NOTE: Contact AMI for custom PLL frequencies
27
XTUNE Range
0-2 V
8-pin (0.150″ ) SOIC
Figure 2: Block Diagram
XIN
XOUT
XTUNE
VCXO
ISO9001
PLL DIVIDER CLK
FS6128
4.24.00
1 page  
AMERICAN MICROSYSTEMS, INC.
FS6128-01
PLL Clock Generator IC with VCXO
April 2000
Table 6: AC Timing Specifications
Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3σ f rom typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN. TYP. MAX. UNITS
Overall
VCXO Stabilization Time *
PLL Stabilization Time *
Synthesis Error
Clock Output (CLK)
Duty Cycle *
Jitter, Period (peak-peak) *
Jitter, Long Term (σy(τ )) *
Rise Time *
Fall Time *
tVCXOSTB
tPLLSTB
From power valid
From VCXO stable
(unless otherwise noted in Frequency Table)
10 ms
500 us
0 ppm
Ratio of high pulse width (as measured from rising
edge to next falling edge at VDD/2) to one clock period
45
55
tj(∆P)
From rising edge to next rising edge at VDD/2,
CL = 10pF
tj(LT)
From 0-500µs at VDD/2, CL = 10pF
compared to ideal clock source
390
155
tr VDD = 3.3V; VO = 0.3V to 3.0V; CL = 10pF
1.7
tf VDD = 3.3V; VO = 3.0V to 0.3V; CL = 10pF
1.7
%
ps
ps
ns
ns
ISO9001
5
4.24.00
5 Page | ||
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