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PDF NCN6000 Data sheet ( Hoja de datos )
| Número de pieza | NCN6000 | |
| Descripción | Compact Smart Card Interface IC | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCN6000
Compact Smart Card
Interface IC
The NCN6000 is an integrated circuit dedicated to the smart card
interface applications. The device handles any type of smart card
through a simple and flexible microcontroller interface. On top of that,
due to the built−in chip select pin, several couplers can be connected in
parallel. The device is particularly suited for low cost, low power
applications, with high extended battery life coming from extremely
low quiescent current.
http://onsemi.com
MARKING
DIAGRAM
Features
• 100% Compatible with ISO7816−3 and EMV Standard
• Wide Battery Supply Voltage Range: 2.7 v Vbat v 6.0 V
• Programmable CRD_VCC Supply to Cope with either 3.0 V or 5.0 V
Card Operation
• Built−in DC−DC Converter Generates the CRD_VCC Supply with a
Single External Low Cost Inductor only, providing a High Efficiency
Power Conversion
• Full Control of the Power Up/Down Sequence Yields High Signal
Integrity on both the Card I/O and the Signal Lines
• Programmable Card Clock Generator
• Built−in Chip Select Logic allows Parallel Coupling Operation
• ESD Protection on Card Pins (8.0 kV, Human Body Model)
• Fault Monitoring includes Vbatlow and Vcclow, providing Logic
Feedback to External CPU
• Card Detection Programmable to Handle Positive or Negative
Going Input
• Built−in Programmable CRD_CLK Stop Function Handles both
High or Low State
• These are Pb−Free Devices**
Typical Application
• E−Commerce Interface
• ATM Smart Card
• Pay TV System
20
TSSOP−20
1 DTB SUFFIX
CASE 948E
NCN
6000
ALYWG
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
A0 1
A1 2
PGM 3
PWR_ON 4
STATUS 5
CS 6
RESET 7
I/O 8
INT 9
CLOCK_IN 10
(Top View)
20 Vbat
19 Lout_H
18 Lout_L
17 PWR_GND
16 GROUND
15 CRD_VCC
14 CRD_IO
13 CRD_CLK
12 CRD_RST
11 CRD_DET
ORDERING INFORMATION
Device
Package
Shipping†
MICRO
CONTROLLER
NCN6000
SMART CARD
INTERFACE
ISO/EMV
NCN6000DTB
TSSOP−20* 75 Units / Rail
NCN6000DTBG TSSOP−20* 75 Units / Rail
NCN6000DTBR2 TSSOP−20* 2500/Tape & Reel
NCN6000DTBR2G TSSOP−20* 2500/Tape & Reel
Figure 1. Simplified Application
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*This package is inherently Pb−Free.
**For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 4
1
Publication Order Number:
NCN6000/D
1 page  
NCN6000
The programming can be achieved with the card powered
ON or OFF. The identification of the interrupt is carried out
by polling the STATUS pin, the Vbat voltage and the
DC−DC results being provided on the same pin as depicted
by the table in Figure 4. During the programming mode, the
PGM pin can be released to High since the mode is internally
latched by the Negative going transition presents on the Chip
Select pin.
CRD_DET
INT
CS
PGM
INTERRUPT
ACKNOWLEDGE
50 ms
CARD IDENTIFICATION
POLLING
CARD EXTRACTED
50 ms
High
A0
A1
STATUS
Low
Low
S1 CLEAR INTERRUPT
S2 CARD PRESENT: STATUS = 1
S3 CLEAR INTERRUPT
S4 CARD PRESENT: STATUS = 0
Figure 5. Interrupt Servicing and Card Polling
When a card is either inserted or extracted, the CRD_DET
pin signal is debounced internally prior to pull the INT pin
to Low. The built−in logic circuit automatically
accommodates positive or negative input signal slope, on
both insertion and extraction state, depending upon the
polarity defined during the initialization sequence. The
default condition is Normally Open switch, negative going
card detection. The external CPU shall acknowledge the
request by forcing CS = L which, in turn, releases the INT
pin to High upon positive going of Chip Select (Table 4).
Polling the STATUS pin as depicted in Table 3 identifies the
active card. If a card is present, the STATUS returns High,
otherwise a Low is presented pin 5. The 50 ms digital filter
is activated during both Insertion and Extraction of the card.
The MPU shall clear the INT line when the card has been
extracted, making the interrupt function available for other
purposes. However, neither the NCN6000 operation nor the
smart card I/O line or commands are affected by the state of
the INT pin.
On the other hand, clearing the INT and reading the
STATUS register can be performed by a single read by the
MPU: states S1 and S2 can be combined in a single
instruction, the same for S3 and S4.
http://onsemi.com
5
5 Page 
NCN6000
SMART CARD SECTION (−25°C to +85°C ambient temperature, unless otherwise noted.)
Rating
Symbol
Pin
Min
CRD_RST @ CRD_VCC = +5.0 V
Output RESET VOH @ Icrd_rst = −20 mA
Output RESET VOL @ Icrd_rst = 200 mA
Output RESET Rise Time @ Cout = 30 pF
Output RESET Fall Time @ Cout = 30 pF
VOH
VOL
tR
tF
12
CRD_VCC − 0.9
0
CRD_RST @ Vcc = +3.0 V
Output RESET VOH @ Icrd_rst = −20 mA
Output RESET VOL @ Icrd_rst = 200 mA
Output RESET Rise Time @ Cout = 30 pF
Output RESET Fall Time @ Cout = 30 pF
CRD_CLK @ CRD_VCC = +3.0 V or +5.0 V
VOH
VOL
tR
tF
CRD_VCC − 0.9
0
13
Typ
−
−
Max
CRD_VCC
0.4
100
100
CRD_VCC
0.4
100
100
Unit
V
V
ns
ns
V
V
ns
ns
CRD_VCC = +5.0 V
Output Frequency (See Note 8)
Output Duty Cycle @ DC Fin = 50% "1%
Output CRD_CLK Rise Time @ Cout = 30 pF
Output CRD_CLK Fall Time @ Cout = 30 pF
Output VOH @ Icrd_clk = −20 mA
Output VOL @ Icrd_clk = 100 mA
FCRDCLK
FCRDDC
tR
tF
VOH
VOL
45
3.15
0
5.0
55
18
18
CRD_VCC
+0.5
MHz
%
ns
ns
V
V
CRD_VCC = +3.0 V
Output Frequency (See Note 8)
Output Duty Cycle @ DC Fin = 50% "1%
Output CRD_CLK Rise Time @ Cout = 30 pF
Output CRD_CLK Fall Time @ Cout = 30 pF
Output VOH @ Icrd_clk = −20 mA @ Cout = 30 pF
Output VOL @ Icrd_clk = 100 mA @ Cout = 30 pF
CRD_I/O @ CRD_VCC = +5.0 V
CRD_I/O Data Transfer Frequency
CRD_I/O Rise Time @ Cout = 30 pF
CRD_I/O Fall Time @ Cout = 30 pF
Output VOH @ Icrd_i/o = −20 mA
Output VOL @ Icrd_i/o = 500 mA, VIL = 0 V
FCRDCLK
FCRDDC
tR
tF
VOH
VOL
FIO
TRIO
TFIO
VOH
VOL
40
1.85
0
14
315
CRD_VCC − 0.9
0
5.0
60
18
18
CRD_VCC
0.7
0.8
0.8
CRD_VCC
0.4
MHz
%
ns
ns
V
V
kHz
ms
ms
V
V
CRD_I/O @ CRD_VCC = +3.0 V
CRD_I/O Data Transfer Frequency
CRD_I/O Rise Time @ Cout = 30 pF
CRD_I/O Fall Time @ Cout = 30 pF
Output VOH @ Icrd_i/o = −20 mA
Output VOL @ Icrd_i/o = 500 mA, VIL = 0 V
CRD_IO Pull Up Resistor @ PWR_ON = H
Card Detection Debouncing Delay:
Card Insertion
Card Extraction
Card Insertion or Extraction Positive Going Input
High Voltage
FIO
TRIO
TFIO
VOH
VOL
RCRDPU
TCRDIN
TCRDOFF
VIHDET
315
CRD_VCC − 0.9
0
14 14
11
50
50
11 0.70 * Vbat
20
−
−
0.8
0.8
CRD_VCC
0.4
26
150
150
Vbat
kHz
ms
ms
V
V
kW
ms
ms
V
Card Insertion or Extraction Negative Going Input
Low Voltage
VILDET
11
0
− 0.30 * Vbat V
Card Detection Bias Pull Up Current @
Vbat = 5.0 V
IDET
11
−
10 − mA
Output Peak Max Current Under Card Static
Operation Mode @ Vcc = 3.0 V or Vcc = 5.0 V
Icrd_iorst 12, 14
−
− 15 mA
Output Peak Max Current Under Card Static
Operation Mode @ Vcc = 3.0 V or Vcc = 5.0 V
Icrd_clk
13
−
− 70 mA
8. The CRD_CLK clock can operate up to 20 MHz, but the rise and fall time are not guaranteed to be fully within the ISO7816 specification over
the temperature range. Typically, tr and tf are 12 ns @ CRD_CLK = 10 MHz.
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11
11 Page | ||
| Páginas | Total 36 Páginas | |
| PDF Descargar | [ Datasheet NCN6000.PDF ] | |
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