PDF XRT4500 Data sheet ( Hoja de datos )

Número de pieza	XRT4500
Descripción	MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
Fabricantes	Exar Corporation
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No Preview Available ! www.DataSheet4U.com áç XRT4500 SEPTEMBER 2002 MULTIPROTOCOL SERIAL NETWORK INTERFACE IC REV. 1.0.7 GENERAL DESCRIPTION The XRT4500 is a fully integrated multiprotocol serial interface. It supports all of the popular serial commu- nication interface standards such as ITU-T V.35, ITU- T V.36, EIA530A, RS232 (ITU-T V.28), ITU-T X.21 and RS449. It can easily be interfaced with most common types of Serial Communications Controllers (SCCs). This device contains eight receivers and eight transmitters, in groups of six or seven. It is a complete solution containing all of the required source and load termination resistors in one 80-pin TQFP package. The XRT4500 operates at higher speeds (20MHz for V.35 and 256kbps for V.28). The XRT4500 can be configured to operate in one of the seven interface standards in either DTE, or DCE modes of operation and power down mode. It fully supports echoed clock as well as clock and data in- version. Loopbacks are supported in DTE and DCE modes of operation. This feature eliminates the need for external circuitry for loopback implementation. Control signals such as RI, RL, DCD, DTR, DSR are protected against glitches by internal filters. These fil- ters can be turned off. The XRT4500 provides an in- ternal oscillator (clock signal) which can be used to conduct standalone diagnostics of DTE equipment. BLOCK DIAGRAM Electrical Interfaces V.10, V.11, V.35, V.28 V.10, V.11, V.35, V.28 V.10, V.11, V.35, V.28 High Speed Transceiver RX1 TX1 RX2 TX2 RX3 TX3 Handshaking/Control Transceivers Signals TXD, RXD High Speed Data and Clock TXC, RXC High Speed Data and Clock SCTE Signals: DCE Transmitter, DTE Receiver V.10, V.11, ---- , V.28 RX4 TX4 RTS, CTS V.10, V.11, ---- , V.28 V.10, V.11, ---- , V.28 RX5 TX5 RX6 TX6 Diagnostic Transceivers DTR, DSR DCD Signals: DCE Transmitter, DTE Receiver FEATURES • Pin Programmable Multiprotocol Serial Interface • V.35, V.36, EIA-530 A, RS232 (V.28), V.10, V.11, X.21 and RS449 Communication Interface Standards • V.28, V.10, V.11 and V.35 Electrical Interfaces are ‘CTR2’ Compliant • Contains On-Chip Source and Load Termination Resistors • Contains Eight Receivers and Eight Transmitters with Switchable DTE and DCE Modes • Glitch Filters on the Control Signals (Selectable) • +5V Single Power Supply with internal DC-DC Converter • Full Support of Loopbacks, Data & Clock Inversion, and Echoed Clock in DTE and DCE Modes • Full Support of Most Popular Types of HDLC Control- lers (Single, Double, and Triple Clocks supported) • High-speed V.28 Driver: 256KHz • Internal Oscillator for Standalone DTE Loopback Testing • Control Signals Can Be Registered and Non-regis- tered • Control Signals Can Be Tri-stated for Bus-based Designs • “Cable Safe” Operation Supported • ESD Protection Over ± 1KV Range • TTL Level Digital Inputs • TTL/CMOS Digital Outputs APPLICATIONS • Data Service Units (DSU) • Channel Service Units (CSU) • Routers • Bridges • Access Equipment V.10, ---- , ---- , V.28 RX7 TX7 LL, RL, RI (TM) V.10, ---- , ---- , V.28 RX8 TX8 LL, RL, RI (TM) Mode and Configuration Control Switching Regulator DC-DC Converter Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 1 page XRT4500 MULTIPROTOCOL SERIAL NETWORK INTERFACE IC REV. 1.0.7 áç FIGURE 22. ILLUSTRATION OF A “2-CLOCK DTE/DCE” INTERFACE ............................................................................ 51 FIGURE 23. THE BEHAVIOR OF THE TXC AND TXD SIGNALS AT THE DCE AND DTE SCCS, (DATA RATE = 1.0MBPS, “DCE- TO-DTE” PROPAGATION DELAY = 160NS, “DTE-TO-DCE” PROPAGATION DELAY = 160NS)............................ 52 FIGURE 24. THE BEHAVIOR OF THE TXC AND TXD SIGNALS AT THE DCE AND DTE SCCS (DATA RATE = 1.544MBPS, DCE- TO-DTE PROPAGATION DELAY = 160NS, DTE-TO-DCE PROPAGATION DELAY = 160NS) ............................. 52 FIGURE 25. ILLUSTRATION OF THE “ECHO-CLOCK” FEATURE WITHIN THE XRT4500 ................................................... 53 FIGURE 26. ILLUSTRATION OF THE WAVE-FORMS, ACROSS A DCE/DTE INTERFACE, WHEN THE ECHO-CLOCK FEATURE (WITHIN THE XRT4500) IS USED AS DEPICTED IN FIGURE 25........................................................................ 54 1.3.5 THE “2CK/3CK” (2-CLOCK/3-CLOCK MODE - ENABLE/DISABLE SELECT INPUT PIN) ..................................... 54 FIGURE 27. ILLUSTRATION OF THE DCE/DTE INTERFACE, WITH THE DCE MODE XRT4500 OPERATING IN THE “2-CLOCK” MODE ........................................................................................................................................................ 55 1.3.6 THE “CLOCK INVERSION” (CK_INV) FEATURE ..................................................................................................... 55 FIGURE 28. ILLUSTRATION OF THE DCE MODE XRT4500 BEING CONFIGURED TO INVERT THE TXC SIGNAL................ 56 FIGURE 29. ILLUSTRATION OF THE DTE MODE XRT4500 BEING CONFIGURED TO INVERT THE TXC SIGNAL ................ 56 FIGURE 30. ILLUSTRATION OF THE DCE MODE XRT4500, WHICH IS OPERATING IN THE “2-CLOCK” MODE, AND INVERTING THE “TXC” SIGNAL ..................................................................................................................................... 57 1.3.7 THE LATCH MODE OF OPERATION ........................................................................................................................ 58 1.3.8 THE REGISTERED MODE OF OPERATION ............................................................................................................. 58 FIGURE 31. AN ILLUSTRATION OF THE EFFECTIVE INTERFACE BETWEEN THE XRT4500 AND THE SCC/MICROPROCESSOR WHEN THE “REGISTERED” MODE IS ENABLED ............................................................................................... 58 FIGURE 32. AN ILLUSTRATION OF THE NECESSARY GLUE LOGIC REQUIRED TO DESIGN A FEATURE SIMILAR TO THAT OFFERED BY THE “REGISTERED” MODE, WHEN USING A DIFFERENT MULTI-PROTOCOL SERIAL NETWORK INTERFACE IC 59 1.3.9 THE INTERNAL OSCILLATOR .................................................................................................................................. 59 FIGURE 33. ILLUSTRATION OF THE INTERNAL OSCILLATORS WITHIN THE XRT4500..................................................... 60 1.3.10 GLITCH FILTERS...................................................................................................................................................... 60 1.3.11 DATA INVERSION .................................................................................................................................................... 60 1.3.12 DATA INTERLUDE ................................................................................................................................................... 60 2.0 RECEIVER AND TRANSMITTER SPECIFICATIONS .........................................................................60 3.0 V.10\V.28 OUTPUT PULSE RISE AND FALL TIME CONTROL .........................................................60 FIGURE 34. V.10 RISE/FALL TIME AS A FUNCTION OF RSLEW ................................................................................. 61 FIGURE 35. V.28 SLEW RATE OVER ± 3 V OUTPUT RANGE WITH 3 KW IN PARALLEL WITH 2500 PF LOAD AS A FUNCTION OF RSLEW................................................................................................................................................ 61 4.0 THE HIGH-SPEED RS232 MODE ........................................................................................................61 5.0 INTERNAL CABLE TERMINATIONS ..................................................................................................62 6.0 OPERATIONAL SCENARIOS ..............................................................................................................62 7.0 APPLICATIONS INFORMATION .........................................................................................................62 FIGURE 36. RECEIVER TERMINATION ........................................................................................................................ 63 TABLE 6: RECEIVER SWITCHES ................................................................................................................................ 63 FIGURE 37. TRANSMITTER TERMINATION .................................................................................................................. 64 TABLE 7: TRANSMITTER SWITCHES........................................................................................................................... 64 FIGURE 38. TYPICAL V.10 OR V.28 INTERFACE (R1 = 10 KW IN V.10 AND 5 KW IN V.28) ........................................ 64 FIGURE 39. TYPICAL V.11 INTERFACE (TERMINATION RESISTOR, R1, IS OPTIONAL.).................................................. 64 FIGURE 40. TYPICAL V.35 INTERFACE ...................................................................................................................... 65 TABLE 8: MUX1 CONNECTION TABLE....................................................................................................................... 65 TABLE 9: MUX2 CONNECTION TABLE (RX4-RX7, TX4-TX7), OUTPUT VERSUS INPUT .............................................. 67 FIGURE 41. SCENARIO A, MUX2, (DCE/DTE = 0, LP = 0)....................................................................................... 68 FIGURE 42. SCENARIO B, MUX2, (DCE/DTE = 0, LP = 1), LOOP BACK NOT ENABLED ............................................. 69 FIGURE 43. SCENARIO C, MUX2, (DCE/DTE = 1, LP = 0)....................................................................................... 70 FIGURE 44. SCENARIO D, MUX2, (DCE/DTE = 1, LP = 1), LOOP BACK NOT ENABLED ............................................. 71 FIGURE 45. SERIAL INTERFACE SIGNALS AND CONNECTOR PIN-OUT ......................................................................... 72 FIGURE 46. SERIAL INTERFACE CONNECTOR DRAWINGS........................................................................................... 73 FIGURE 47. EIA-530 CONNECTION DIAGRAM FOR XRT4500 .................................................................................... 74 FIGURE 48. RS-232 CONNECTION DIAGRAM FOR XRT4500 ..................................................................................... 75 Scenarios 1 & 2 Normal: ‘3-clock’ DCE/DTE Interface Operation ...........................................................76 Input Pin Settings ....................................................................................................................................76 Scenario 3 &2 DTE Loop-Back Mode......................................................................................................77 Input Pin Settings ....................................................................................................................................77 Scenario 4 ...............................................................................................................................................78 Comments: DCE Loop-Back Mode .........................................................................................................78 II 5 Page XRT4500 MULTIPROTOCOL SERIAL NETWORK INTERFACE IC REV. 1.0.7 áç PIN DESCRIPTIONS (CONT.) PIN Signal # 18 LP 19 TX8O 20 VDD 21 CPP 22 CPM DTE MODE RLA DCE MODE TYPE FUNCTION I Loopback Command Input Pin – Active Low: This active-low input pin permits the user to configure the XRT4500 into a “Loop-Back” Mode. The exact loop-back will depend upon whether the XRT4500 is operating in the DTE or DCE Modes. Setting this input pin to “LOW” enables the Loop-back Operation. Setting this input pin to “HIGH” disables the Loop-back Operation. This input pin contains an Internal 20KΩ pull-up to VDD. RIA O Transmitter 8 – Single Ended Data Output to Line The XRT4500 accepts a TTL level binary data stream, from the local terminal equipment via the “TX8D” input pin (pin 17), and outputs it, in either a V.10 or V.28 manner via this output pin. The exact role that this output pin plays depends upon whether the XRT4500 is operating in the DTE or DCE Modes. If the XRT4500 is configured to operate in the DCE Mode: This output pin will typically drive the state of either the “RI” (Ring Indicator) or “TM” (Test Mode) signals to the Remote Terminal Equipment. If the XRT4500 is configured to operate in the DTE Mode: This output pin will typically drive the state of the “RL” (Remote Loop-back) signal to the Remote Terminal Equipment. Analog VDD – For Receivers 4, 5, 6, 7 and 8. Charge Pump Capacitor Pin: A 2.2µF tantalum capacitor must be connected between pin 21 and pin 22. Charge Pump Capacitor Pin: A 2.2µF tantalum capacitor must be connected between pin 21 and pin 22. NOTE: Signal names beginning with D_ are digital signals. NOTE: Signal names ending with B and A are the positive and negative polarities of differential signals respectively. 8 11 Page

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