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PDF MC1251A Data sheet ( Hoja de datos )

Número de pieza MC1251A
Descripción (MC1x51A) Advanced Step Motor Control Chipset
Fabricantes PMD 
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Advanced Step Motor MC1451A, MC1451A-E
Control Chipset
MC1251A, MC1251A-E
MC1151A, MC1151A-E
Features
Advanced control of up to 4 step motors
per chipset
High speed pulse and direction output
S-curve, trapezoidal, velocity contouring,
and electronic gearing trajectory modes
Optional incremental encoder feedback
Software & feature compatible with other
versions of PMD's chipset family
Available in 1, 2, or 4 axis configurations
32-bit position, velocity, acceleration and
jerk trajectory profile registers
Pulse and direction output for each axis at
up to 1.5 Mpulses/sec
On-the-fly stall detection
Two travel-limit switches per axis
External motion breakpoint per axis
Intelligent easy-to-use packet-oriented
command protocol
Programmable pulse output modes
Chipset Developer's kit available
Typical Configuration
Host
Processor
General Description
The MC1451A is a dedicated motion processor which functions
as a complete chip-based step motor controller. Packaged in a
2-IC chipset, this device performs trajectory generation and
pulse and direction signal generation for use in a wide variety of
stepper-based systems. The MC1451A provides an optional
third IC which allows incremental encoder signal input for
position verification and on-the-fly stall detection. The MC1451A
is available in a one, a two, and a four-axis configuration.
The MC1451A is functionally similar to other PMD motion
processors however it is dedicated to the control of step motors,
instead of servo motors. All of these devices provide
sophisticated trajectory generation and synchronization features
allowing the creation of complex motion sequences.
Amp
M E Axis 1
In addition to pulse and direction circuitry which can output at
up to 1.5 megapulses per second the chipset provides two limit
switches per axis, a programmable external signal breakpoint
per axis, and an 'At Rest' output signal.
MC1451A
(I/O & CP
& ENC)
Amp
Amp
M E Axis 2
The chipset is controlled by a host processor which interfaces
with the chipset via an 8-bit bi-directional port. Communications
(MC1451A, MC1251A to/from the chipset consist of packet-oriented messages. A host
only) interrupt line is provided so that the chipset can signal the host
when special conditions occur such as stall detection.
M E Axis 3
(MC1451A only)
The chipset is packaged in 2 68-pin PLCC packages. An
optional third 44 pin PLCC chip provides encoder input. All
chips are CMOS and are powered by 5 volts.
Amp M E Axis 4
(MC1451A only)
Doc. Rev. 12.02, Nov. 1997
Performance Motion Devices, Inc. 12 Waltham St. Lexington, MA 02421 tel: 781.674.9860 fax: 781.674.9861 www.pmdcorp.com

1 page




MC1251A pdf
Absolute Maximum Ratings
Unless otherwise stated, all electrical specifications are for both
the I/O and CP chips.
Storage Temperature, Ts .................... -55 deg. C to +150 deg. C
Supply Voltage, Vcc ............................ -0.3 V to +7.0 V
Power Dissipation, Pd ......................... 650 mW (I/O and CP
combined)
Operating Ratings
Operating Temperature, Ta .................0 deg. C to +70 deg. C*
Nominal Clock Frequency, Fclk ...........25.0 Mhz
Supply Voltage, Vcc.............................4.75 V to 5.25 V
* Industrial and Military operating ranges also available. Contact your
PMD representative for more information.
DC Electrical Characteristics
(Vcc and Ta per operating ratings, Fclk = 25.0 Mhz)
Symbol
Vcc
Idd
Input Voltages
Vih
Vil
Vihclk
Vihreset
Output Voltages
Voh
Parameter
Supply Voltage
Supply Current
Logic 1 input voltage
Logic 0 input voltage
Logic 1 voltage for clock pin
(ClkIn)
Logic 1 voltage for reset pin
(reset)
Logic 1 Output Voltage
Vol Logic 0 Output Voltage
Iout Tri-State output leakage current
Iin Input current
Iinclk Input current ClkIn
AC Electrical Characteristics
(see reference timing diagrams)
(Vcc and Ta per operating ratings; Fclk = 25.0 Mhz)
(~ character indicates active low signal)
Timing Interval
Encoder and Index Pulse Timing
Motor-Phase Pulse Width
Dwell Time Per State
Index Pulse Setup and Hold
(relative to Quad A and Quad B low)
Reset Timing
Stable Power to Reset
Reset Low Pulse Width
Clock Timing
Clock Frequency (Fclk)
Clock Pulse Width
Clock Period
T#
T1
T2
T3
T4
T5
Min. Max. Units
4.75 5.25 V
100 mA
2.0
Vcc + 0.3
V
-0.3 0.8 V
3.0
Vcc+0.3
V
4.0
Vcc+0.3
V
2.4 V
0.33 V
-20 20 uA
-50 50 uA
-20 20 uA
Min. Max.
1.6
0.8
0
0.25
1.0
6.7 25.6
19.5 75 (note 2)
39 149 (note 2)
Conditions
open outputs
@CP Io = 300 uA
@I/O Io = 4 mA
@CP Io = 2 mA
@I/O Io = 4 mA
0 < Vout < Vcc
0 < Vi < Vcc
0 < Vi < Vcc
Units
uS
uS
uS
Sec
uS
Mhz
nS
nS
5

5 Page





MC1251A arduino
Pinouts
9 1 61
10
I/O
(Top view)
26
27
43
9 1 61
60 10
44 26
CP
(Top view)
60
7
17
44
27 43
(Chip Outlines Not Drawn To Scale)
6 1 40
ENC
(Top view)
18 28
39
29
MC1451A & MC1451A-E Pinouts
4, 21, 25, 38, 55
4, 22, 33
VCC
CPCntrl2
22
VCC
CPCntrl3
63
Data2
58
HostCmd
41
Data3
57
28 Pulse1
HostRdy
37
Data4
50
42 Dir1
HostRead
51
Data5
49
13 Home1
HostWrite
47
Data6
46
26 Pulse2
HostSlct
48
Data7
43
30 Dir2
HostIntrpt 44 56 AtRest1
Data8
40
23 Home2
HostData0 50 55 AtRest2
Data9
39
40 Pulse3
HostData1 61 54 AtRest3
Data10
36
35 Dir3
HostData2 53 53 AtRest4
Data11
35
I/O11 Home3
39 Pulse4
HostData3 65 24 ClkIn
HostData4 67 19 ClkOut
CP I/OAddr0
I/OAddr1
28
9
34 Dir4
HostData5 62 17 Reset
I/OAddr2
6
10 Home4
HostData6 64 16 I/OCntrl0
I/OAddr3
5
46 CPClk
HostData7 60 18 I/OCntrl1
I/OWrite
15
52 I/OClkIn
CPData4 18 68 I/OCntrl2
PosLimit1
52
45 I/OClkOut
CPData5 5 67 I/OCntrl3
PosLimit2
45
29 CPAddr2
CPData6
6
PosLimit3
42
12 CPAddr3
CPData7
7
PosLimit4
38
2 CPWrite
CPData8
8
NegLimit1
51
20 CPCntrl0
CPData9
17
NegLimit2
44
36 CPCntrl1
CPData10
3
NegLimit3
41
43 CPReset
CPData11
1
NegLimit4
37
CPAddr0
68
GND
CPAddr1
27
GND
14, 15, 32, 49, 54, 66
3, 34
3, 14, 16, 25, 35
VCC
CPAddr0 24
CPAddr2 20
30 QuadA1
CPAddr3 23
36 QuadB1
CPWrite 13
17 QuadA2
CPCntrl0 15
18 QuadB2
CPData2 22
ENC27 QuadA3
28 QuadB3
CPData3
CPData4
19
9
5 QuadA4
CPData5 31
29 QuadB4
CPData6 41
7 CPClk
CPData7 42
33 I/OClkIn
CPData8 44
6 I/OClkOut
CPData9
1
CPData10 12
CPData11
2
GND
10, 21, 32, 34, 43
11

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