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PDF ICS87931I Data sheet ( Hoja de datos )
| Número de pieza | ICS87931I | |
| Descripción | LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER | |
| Fabricantes | ICS | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
GENERAL DESCRIPTION
The ICS87931I is a low voltage, low skew
,&6 LVCMOS/LVTTL Clock Multiplier/Zero Delay
HiPerClockS™ Buffer and a member of the HiPerClockS™ family
of High Performance Clock Solutions from ICS.
With output frequencies up to 150MHz, the
ICS87931I is targeted for high performance clock applications.
Along with a fully integrated PLL, the ICS87931I contains fre-
quency configurable outputs and an external feedback input for
regenerating clocks with “zero delay”.
Selectable clock inputs, CLK1 and differential CLK0, nCLK0
support redundant clock applications. The CLK_SEL input de-
termines which reference clock is used. The output divider val-
ues of Bank A, B and C are controlled by the DIV_SELA,
DIV_SELB and DIV_SELC, respectively.
For test and system debug purposes, the PLL_SEL input al-
lows the PLL to be bypassed. When LOW, the nMR input re-
sets the internal dividers and forces the outputs to the high im-
pedance state.
The effective fanout of the ICS87931I can be increased to 12
by utilizing the ability of each output to drive two series termi-
nated transmission lines.
FEATURES
• Fully integrated PLL
• 6 LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock
for redundant clock applications
• Maximum output frequency: 150MHz
• VCO range: 220MHz to 480MHz
• External feedback for “zero delay” clock regeneration
• Output skew, Same Frequency: 300ps (maximum)
• Output skew, Different Frequency: 400ps (maximum)
• Cycle-to-cycle jitter: 100ps (maximum)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Pin compatible with MPC931
PIN ASSIGNMENT
BLOCK DIAGRAM
POWER_DN Pullup
PLL_SEL Pullup
CLK_SEL Pulldown
CLK1 Pullup
nc
VDDA
POWER_DN
CLK1
nMR
CLK0
nCLK0
GND
32 31 30 29 28 27 26 25
1 24
2 23
3 ICS87931I 22
4
32-Lead LQFP
21
5 7mm x 7mm x 1.4mm 20
6 package body 19
7
Y package
18
Top View
8 17
9 10 11 12 13 14 15 16
GND
QB0
QB1
VDDO
EXTFB_SEL
CLK_SEL
PLL_SEL
nc
CLK0 Pullup
nCLK0 None
EXTFB_SEL Pulldown
EXT_FB Pullup
DIV_SELA Pulldown
DIV_SELB Pulldown
CLK_EN0
CLK_EN1
DIV_SELC
Pullup
Pullup
Pulldown
nMR Pullup
87931BYI
1
0
PHASE
DETECTOR
VCO
0
0
1
÷2 1
LPF
1
÷8
0
POWER-ON RESET
DISABLE
LOGIC
www.icst.com/products/hiperclocks.html
1
÷2/÷4
÷2/÷4
÷4/÷6
QA0
QA1
QB0
QB1
QC0
QC1
REV. A JUNE 23, 2003
1 page  
Integrated
Circuit
Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs, VI
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
4.6V
-0.5V to VDDA + 0.5 V
-0.5V to VDDO + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VDDA
V
DDO
IDDA
IDDO
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Output Supply Current
3.135
3.135
3.3
3.3
20
100
Maximum
3.465
3.465
Units
V
V
mA
mA
TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
VIH
Input
High Voltage
DIV_SELA:DIV_SELC,
CLK_EN0, CLK_EN1,
POWER_DN, nMR, CLK_SEL,
PLL_SEL, EXTFB_SEL
Test Conditions
Minimum Typical Maximum Units
2
VDD + 0.3
V
CLK1, EXT_FB
DIV_SELA:DIV_SELC,
CLK_EN0, CLK_EN1,
VIL
Input
POWER_DN, nMR, CLK_SEL,
Low Voltage PLL_SEL, EXTFB_SEL
2 V + 0.3 V
DD
-0.3 0.8 V
CLK1, EXT_FB
-0.3 1.3 V
IIN Input Current
±120
VOH Output High Voltage; NOTE 1
IOH = -20mA
2.4
VOL Output Low Voltage; NOTE 1
IOL = 20mA
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, 3.3V Output Load Test Circuit.
µA
V
V
TABLE 5C. DIFFERENTIAL DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
IIN Input Current
VPP
VCMR
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
NOTE 1, 2
0.15
GND + 0.5
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 is VDDA + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
Maximum
±120
1.3
VDD - 0.85
Units
µA
V
V
87931BYI
www.icst.com/products/hiperclocks.html
5
REV. A JUNE 23, 2003
5 Page 
Integrated
Circuit
Systems, Inc.
ICS87931I
LOW SKEW, 1-TO-6
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on
the component side is preferred. This can reduce unwanted in-
ductance between the decoupling capacitor and the power pin
caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V pin as possible.
DDA
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
• The differential 50Ω output traces should have same
length.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
• Make sure no other signal traces are routed between the
clock trace pair.
• The series termination resistors should be located as
close to the driver pins as possible.
VCCA U1
Pin 1
50 Ohm
Trace
C3 R1
GND
VCC
VIA
Other
signals
C2
87931BYI
C1 R2
50 Ohm
Trace
FIGURE 4B. PCB BOARD LAYOUT FOR ICS87931I
www.icst.com/products/hiperclocks.html
11
REV. A JUNE 23, 2003
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS87931I.PDF ] | |
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