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PDF ISL6545A Data sheet ( Hoja de datos )
| Número de pieza | ISL6545A | |
| Descripción | 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
ISL6545, ISL6545A
March 3, 2011
FN6305.6
5V or 12V Single Synchronous Buck
Pulse-Width Modulation (PWM) Controller
The ISL6545, ISL6545A makes simple work out of
implementing a complete control and protection scheme for a
DC/DC stepdown converter driving N-Channel MOSFETs in a
synchronous buck topology. Since it can work with either 5V or
12V supplies, this one IC can be used in a wide variety of
applications within a system. The ISL6545, ISL6545A
(hereafter referred to as “ISL6545x”, except as needed)
integrates the control, gate drivers, output adjustment,
monitoring and protection functions into a single 8 Ld SOIC or
10 Ld DFN package.
The ISL6545x provides single feedback loop, voltage-mode
control with fast transient response. The output voltage can be
precisely regulated to as low as 0.6V, with a maximum
tolerance of ±1.0% over-temperature and line voltage
variations. A selectable fixed frequency oscillator (ISL6545 for
300kHz; ISL6545A for 600kHz) reduces design complexity,
while balancing typical application cost and efficiency.
The error amplifier features a 20MHz gain-bandwidth
product and 9V/µs slew rate which enables high converter
bandwidth for fast transient performance. The resulting
PWM duty cycles range from 0% to 100%.
Protection from overcurrent conditions is provided by
monitoring the rDS(ON) of the lower MOSFET to inhibit PWM
operation appropriately. This approach simplifies the
implementation and improves efficiency by eliminating the
need for a current sense resistor.
Pinout
ISL6545, ISL6545A
(8 LD SOIC)
TOP VIEW
BOOT 1
UGATE 2
GND 3
LGATE/OCSET 4
8 PHASE
7 COMP/SD
6 FB
5 VCC
ISL6545, ISL6545A
(10 LD 3x3 DFN)
TOP VIEW
BOOT 1
UGATE 2
N/C 3
GND 4
LGATE/OCSET 5
GND
10 PHASE
9 COMP/SD
8 FB
7 N/C
6 VCC
Features
• Operates from +5V or +12V Supply Voltage (for bias)
- 1.0V to 12V VIN Input Range (up to 20V possible with
restrictions; see Input Voltage Considerations)
- 0.6V to VIN Output Range
- Integrated Gate Drivers use VCC (5V to 12V)
- 0.6V Internal Reference; ±1.0% tolerance
• Simple Single-Loop Control Design
- Voltage-Mode PWM Control
- Drives N-Channel MOSFETs
- Traditional Dual Edge Modulator
• Fast Transient Response
- High-Bandwidth Error Amplifier
- Full 0% to 100% Duty Cycle
• Lossless, Programmable Overcurrent Protection
- Uses Lower MOSFET’s rDS(ON)
• Small Converter Size in 8 Ld SOIC or 10 Ld DFN
- 300kHz or 600kHz Fixed Frequency Oscillator
- Fixed Internal Soft-Start, Capable into a Pre-biased
Load
- Integrated Boot Diode
- Enable/Shutdown Function on COMP/SD Pin
- Output Current Sourcing and Sinking
• Pb-Free (RoHS Compliant)
Applications
• Power Supplies for Microprocessors or Peripherals
- PCs, Embedded Controllers, Memory Supplies
- DSP and Core Communications Processor Supplies
• Subsystem Power Supplies
- PCI, AGP; Graphics Cards; Digital TV
- SSTL-2 and DDR/DDR2/DDR3 SDRAM Bus
Termination Supply
• Cable Modems, Set Top Boxes, and DSL Modems
• Industrial Power Supplies; General Purpose Supplies
• 5V or 12V-Input DC/DC Regulators
• Low-Voltage Distributed Power Supplies
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2006, 2007, 2009, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6545, ISL6545A
Electrical Specifications VCC = 12V, TJ = 0 to +85°C. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN MAX
(Note 7) TYP (Note 7)
Upper Gate Source Impedance
Upper Gate Sink Impedance
Lower Gate Source Impedance
Lower Gate Sink Impedance
PROTECTION/DISABLE
RUG-SRCl
RUG-SNKl
RLG-SRCl
RLG-SNKl
VCC = 4.25V; I = 50mA
VCC = 4.25V; I = 50mA
VCC = 4.25V; I = 50mA
VCC = 4.25V; I = 50mA
3.5
2.7
2.75
2.1
OCSET Current Source
IOCSET
ISL6545C; LGATE/OCSET = 0V
ISL6545I; LGATE/OCSET = 0V
19.5
18.0
21.5
21.5
23.5
23.5
Disable Threshold (COMP/SD pin)
VDISABLE
0.375 0.400
NOTE:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
0.425
UNITS
Ω
Ω
Ω
Ω
µA
µA
V
Functional Pin Description (SOIC, DFN)
VCC (SOIC Pin 5, DFN Pin 6)
This pin provides the bias supply for the ISL6545x, as well
as the lower MOSFET’s gate, and the BOOT voltage for the
upper MOSFET’s gate. An internal 5V regulator will supply
bias if VCC rises above 6.5V (but the LGATE/OCSET and
BOOT will still be sourced by VCC). Connect a well-
decoupled 5V or 12V supply to this pin.
FB (SOIC Pin 6, DFN Pin 8)
This pin is the inverting input of the internal error amplifier. Use
FB, in combination with the COMP/SD pin, to compensate the
voltage-control feedback loop of the converter. A resistor divider
from the output to GND is used to set the regulation voltage.
GND (SOIC Pin 3, DFN Pin 4)
This pin represents the signal and power ground for the IC.
Tie this pin to the ground island/plane through the lowest
impedance connection available. For the DFN package,
Pin 4 MUST be connected for electrical GND; the metal pad
under the package should also be connected to the GND
plane for thermal conductivity.
PHASE (SOIC Pin 8, DFN Pin 10)
Connect this pin to the source of the upper MOSFET, and
the drain of the lower MOSFET. It is used as the sink for the
UGATE driver, and to monitor the voltage drop across the
lower MOSFET for overcurrent protection. This pin is also
monitored by the adaptive shoot-through protection circuitry
to determine when the upper MOSFET has turned off.
UGATE (SOIC Pin 2, DFN Pin 2)
Connect this pin to the gate of upper MOSFET; it provides
the PWM-controlled gate drive. It is also monitored by the
adaptive shoot-through protection circuitry to determine
when the upper MOSFET has turned off.
BOOT (SOIC Pin 1, DFN Pin 1)
This pin provides ground referenced bias voltage to the upper
MOSFET driver. A bootstrap circuit is used to create a voltage
suitable to drive an N-channel MOSFET (equal to VCC minus
the on-chip BOOT diode voltage drop), with respect to PHASE.
COMP/SD (SOIC Pin 7, DFN Pin 9)
This is a multiplexed pin. During soft-start and normal converter
operation, this pin represents the output of the error amplifier.
Use COMP/SD, in combination with the FB pin, to compensate
the voltage-control feedback loop of the converter.
Pulling COMP/SD low (VDISABLE = 0.4V nominal) will
shut-down (disable) the controller, which causes the
oscillator to stop, the LGATE and UGATE outputs to be held
low, and the soft-start circuitry to re-arm. The external
pull-down device will initially need to overcome up to 5mA of
COMP/SD output current. However, once the IC is disabled,
the COMP output will also be disabled, so only a 20µA
current source will continue to draw current.
When the pull-down device is released, the COMP/SD pin
will start to rise, at a rate determined by the 20µA charging
up the capacitance on the COMP/SD pin. When the
COMP/SD pin rises above the VDISABLE trip point, the
ISL6545x will begin a new Initialization and soft-start cycle.
LGATE/OCSET (SOIC Pin 4, DFN Pin 5)
Connect this pin to the gate of the lower MOSFET; it provides
the PWM-controlled gate drive (from VCC). This pin is also
monitored by the adaptive shoot-through protection circuitry to
determine when the lower MOSFET has turned off.
During a short period of time following Power-On Reset
(POR) or shut-down release, this pin is also used to
determine the overcurrent threshold of the converter.
Connect a resistor (ROCSET) from this pin to GND. See
“Overcurrent Protection (OCP)” on page 7 for equations. An
overcurrent trip cycles the soft-start function, after two
dummy soft-start time-outs. Some of the text describing the
LGATE function may leave off the OCSET part of the name,
when it is not relevant to the discussion.
N/C (DFN only; Pin 3, Pin 7)
These two pins in the DFN package are No Connect.
5 FN6305.6
March 3, 2011
5 Page 
ISL6545, ISL6545A
C2
COMP
R2 C1
-
E/A +
FB
VREF
R3 C3
R1
Ro
PWM
CIRCUIT
OSCILLATOR
VOSC
HALF-BRIDGE
DRIVE
VIN
UGATE
PHASE
LGATE
L
VOUT
D
C
E
ISL6545x EXTERNAL CIRCUIT
FIGURE 9. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of VOUT/VCOMP. This function is dominated by a DC
gain, given by dMAXVIN/VOSC, and shaped by the output
filter, with a double pole break frequency at FLC and a zero at
FCE. For the purpose of this analysis, L and D represent the
channel inductance and its DCR, while C and E represent the
total output capacitance and its equivalent series resistance.
FLC=
-------------1--------------
2π ⋅ L ⋅ C
FCE= 2----π-----⋅--1-C------⋅---E--
(EQ. 3)
The compensation network consists of the error amplifier
(internal to the ISL6545x) and the external R1-R3, C1-C3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F0; typically 0.1 to 0.3 of FSW) and adequate phase
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F0dB and 180°. The
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 9. Use the following guidelines for locating the
poles and zeros of the compensation network:
1. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate
value for R2 for desired converter bandwidth (F0). If
setting the output voltage via an offset resistor connected
to the FB pin, Ro in Figure 9, the design procedure can
be followed as presented.
R2
=
---V----O-----S----C-----⋅---R-----1-----⋅---F----0----
dMAX ⋅ VIN ⋅ FLC
(EQ. 4)
2. Calculate C1 such that FZ1 is placed at a fraction of the FLC,
at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio FCE/FLC, the lower the FZ1
frequency (to maximize phase boost at FLC).
C1
=
-----------------------1------------------------
2π ⋅ R2 ⋅ 0.5 ⋅ FLC
(EQ. 5)
3. Calculate C2 such that FP1 is placed at FCE.
C2
=
-------------------------C-----1---------------------------
2π ⋅ R2 ⋅ C1 ⋅ FCE – 1
(EQ. 6)
4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3
such that FP2 is placed below FSW (typically, 0.5 to 1.0
times FSW). FSW represents the switching frequency.
Change the numerical factor to reflect desired placement
of this pole. Placement of FP2 lower in frequency helps
reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at
the COMP pin and minimizing resultant duty cycle jitter.
R3
=
--------R----1---------
F----S----W----
FLC
–
1
C3
=
------------------------1-------------------------
2π ⋅ R3 ⋅ 0.7 ⋅ FSW
(EQ. 7)
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The equations shown in Equations 8
and 9 describe the frequency response of the modulator
(GMOD), feedback compensation (GFB) and closed-loop
response (GCL):
GMOD(f)
=
-d---M-----A----X-----⋅---V----I--N-- ⋅ --------------------------1-----+-----s----(--f--)----⋅---E-----⋅---C-----------------------------
VOSC 1 + s(f) ⋅ (E + D) ⋅ C + s2(f) ⋅ L ⋅ C
GFB(f)
=
-----1-----+-----s----(--f--)----⋅---R----2-----⋅---C-----1-------
s(f) ⋅ R1 ⋅ (C1 + C2)
⋅
⋅ -------------------------------1-----+-----s---(--f---)---⋅---(---R----1-----+-----R-----3----)---⋅---C-----3--------------------------------
(
1
+
s
(
f
)
⋅
R3
⋅
C
3)
⋅
⎝⎛ 1
+
s(f)
⋅
R
2
⋅
⎛
⎝
C-C----1-1----+-⋅---C-C----2-2--⎠⎞⎠⎞
(EQ. 8)
GCL(f) = GMOD(f) ⋅ GFB(f)
where, s(f) = 2π ⋅ f ⋅ j
COMPENSATION BREAK FREQUENCY EQUATIONS
FZ1 = 2----π-----⋅---R---1--2-----⋅---C-----1-
FP1 = 2----π-----⋅---R-----2-----⋅1-----C----------1---------⋅------C----------2------
C1 + C2
FZ2
=
-------------------------1--------------------------
2π ⋅ (R1 + R3) ⋅ C3
FP2
=
---------------1----------------
2π ⋅ R3 ⋅ C3
(EQ. 9)
11 FN6305.6
March 3, 2011
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ISL6545A.PDF ] | |
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