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PDF PPG33F Data sheet ( Hoja de datos )

Número de pieza PPG33F
Descripción 3-BIT PROGRAMMABLE PULSE GENERATOR
Fabricantes Data Delay Devices 
Logotipo Data Delay Devices Logotipo



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No Preview Available ! PPG33F Hoja de datos, Descripción, Manual

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3-BIT PROGRAMMABLE
PULSE GENERATOR
(SERIES PPG33F)
PPG33F
ddaeltaay 3
devices, inc.
FEATURES
PACKAGES
Digitally programmable in 7 steps
Monotonic pulse-width-vs-address variation
Rising edge triggered
Two separate outputs: inverting & non-inverting
Precise and stable pulse width
Input & outputs fully TTL interfaced & buffered
10 T2L fan-out capability
Fits standard 14-pin DIP socket
Auto-insertable
TRIG
OUT
N/C
N/C
N/C
RES
GND
1 14 VCC
2 13 OUT/
3 12 N/C
4 11 N/C
5 10 A0
6 9 A1
7 8 A2
DIP
PPG33F-xx Commercial
PPG33F-xxM Military
TRIG 1 16 VCC
N/C 2 15 OUT/
OUT 3 14 N/C
N/C 4 13 N/C
N/C 5 12 A0
N/C 6 11 A1
RES 7 10 A2
GND 8 9 N/C
Gull-Wing
PPG33F-xxC3 Commercial
PPG33F-xxMC3 Military
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The PPG33F-series device is a 3-bit digitally programmable pulse
TRIG Trigger Input
generator. The width, PWA, depends on the address code (A2-A0)
OUT Non-inverted Output
according to the following formula:
OUT/ Inverted Output
A0-A2 Address Bits
PWA = PW0 + TINC * A
RES Reset
VCC +5 Volts
where A is the address code, TINC is the incremental pulse width of the
GND Ground
device, and PW0 is the inherent pulse width of the device. The
incremental width is specified by the dash number of the device and can range from 0.5ns through 50ns,
inclusively. RESET is held LOW during normal operation. When it is brought HIGH, OUT and OUT/ are
forced into LOW and HIGH states, respectively, and the unit is ready for the next trigger input. The
address is not latched and must remain asserted while the output pulse is active.
SERIES SPECIFICATIONS
Programmed pulse width tolerance: 5% or 1ns,
whichever is greater
Inherent width (PW0): 9ns typical
Inherent delay (TTO): 3.5ns ± 2ns
Operating temperature: 0° to 70° C
Supply voltage VCC: 5VDC ± 5%
Supply current: ICC = 41ma typical
1997 Data Delay Devices
DASH NUMBER SPECIFICATIONS
Part
Number
PPG33F-.5
PPG33F-1
PPG33F-2
PPG33F-3
PPG33F-4
PPG33F-5
PPG33F-6
PPG33F-8
PPG33F-10
PPG33F-20
PPG33F-30
PPG33F-40
PPG33F-50
Incremental Width
Per Step (ns)
0.5 ± 0.3
1 ± 0.4
2 ± 0.4
3 ± 0.5
4 ± 0.5
5 ± 0.6
6 ± 0.7
8 ± 0.8
10 ± 1.0
20 ± 1.5
30 ± 1.8
40 ± 2.0
50 ± 2.5
Total Width
Change (ns)
3.50 ± 1.00
7.00 ± 1.00
14.0 ± 1.00
21.0 ± 1.05
28.0 ± 1.40
35.0 ± 1.75
42.0 ± 2.10
56.0 ± 2.80
70.0 ± 3.50
140 ± 7.00
210 ± 10.5
280 ± 14.0
350 ± 17.5
NOTE: Any dash number between .5 and 50 not
shown is also available.
Doc #97010
1/15/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1

1 page




PPG33F pdf
DELAY LINE AUTOMATED TESTING
PPG33F
TEST CONDITIONS
INPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Input Pulse:
High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance: 50Max.
Rise/Fall Time:
3.0 ns Max. (measured
between 0.6V and 2.4V )
Pulse Width:
PWIN = 10ns
Period:
PERIN = 2 x Max. Pulse Width
OUTPUT:
Load:
Cload:
Threshold:
1 FAST-TTL Gate
5pf ± 10%
1.5V (Rising & Falling)
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
COMPUTER
SYSTEM
PRINTER
PULSE
GENERATOR
OUT
TRIG
IN DEVICE UNDER OUT
TEST (DUT)
REF
IN
TRIG
TIME INTERVAL
COUNTER
Test Setup
INPUT
SIGNAL
OUTPUT
SIGNAL
TRISE
PWIN
PERIN
TFALL
2.4V VIH 2.4V
1.5V
1.5V
0.6V
0.6V
VIL
TTO PWA
1.5V
VOH
1.5V
Timing Diagram For Testing
VOL
Doc #97010
1/15/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
5

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